v1.10.1

What's Changed

• ⚠️ remove redundant JTAG reset signal (TRST) by @stnolting in #928
• minor rtl code clean-ups by @stnolting in #929
• Add UART FIFO clear flags; add DMA FIRQ interrupt configuration by @stnolting in #930
• Minor rtl edits/cleanups by @stnolting in #931
• ⚠️ rework CFU interface by @stnolting in #932
• minor software updates and fixes by @stnolting in #933
• [sw] add auxiliary/helper functions library by @stnolting in #934
• minor rtl edits and cleanups by @stnolting in #935
• Minor sw & hw cleanups by @stnolting in #936
• 🧪 Add experimental XBUS (Wishbone) to AHB3-Lite bridge by @stnolting in #937
• ⚠️ Remove AMO_RVS_GRANULARITY generic by @stnolting in #938
• ⚠️ rework GPTMR by @stnolting in #939

Full Changelog: v1.10.0...v1.10.1

v1.10.0

What's Changed

• Add NEORV32 as Vivado IP by @stnolting in #894
• Cleanup SW library by @stnolting in #900
• Add back Dhrystone port by @stnolting in #901
• Update neorv32_sdi.vhd - Minor typo correction by @ucycg in #903
• Add COE and MEM file generator options by @stnolting in #904
• [FPU] prevent GCC from emitting fused multiply-add instructions by @stnolting in #905
• Add SLINK routing information ports by @stnolting in #908
• Make XIRQ trigger configuration programmable by @stnolting in #911
• Add HDL file list files by @stnolting in #909
• Relocate f files by @stnolting in #912
• Add variable-sized ports to Vivado IP block by @stnolting in #913
• Fix uncached/cached access priority by @stnolting in #915
• [xbus] access type identifier (tag signal) by @stnolting in #917
• [sw/lib] ⚠️ rework gpio_pin_set function by @stnolting in #921
• [rtl] TRNG: add data-available interrupt by @stnolting in #922
• Minor code cleanups by @stnolting in #925
• ✨ Add pre-configured Eclipse example project by @stnolting in #926

New Contributors

• @ucycg made their first contribution in #903

Full Changelog: v1.9.9...v1.10.0

v1.9.9

What's Changed

• minor rtl clean-ups and optimization by @stnolting in #872
• use simplified VHDL file headers by @stnolting in #873
• ⚠️ rename SLINK data interface registers by @stnolting in #874
• ⚠️ simplify XBUS gateway by @stnolting in #876
• [DMA] use FIRQ select instead of FIRQ mask by @stnolting in #877
• rtl logic optimization and cleanups by @stnolting in #880
• fix external debug-halt vs. exception concurrency by @stnolting in #882
• minor rtl fixes by @stnolting in #883
• [rtl] fix single-step halting by @stnolting in #887
• minor rtl cleanups by @stnolting in #889
• Fix UART receiver by @Unike267 in #891

Full Changelog: v1.9.8...v1.9.9

v1.9.8

What's Changed

• CPU RTL optimization by @stnolting in #857
• ⚠️ remove WDT + TRNG interrupts; 🐛 fix bug in core-complex clocking during sleep by @stnolting in #858
• ⚠️ rework ONEWIRE and GPTMR interrupts by @stnolting in #859
• ⚠️ rework TWI interrupt by @stnolting in #860
• 🐛 fix DMA fence flag, ⚠️ rework CPU FIRQs by @stnolting in #864
• Support tool-specific standard flags in makefile by @jpf91 in #862
• ⚠️ rework TWI module by @stnolting in #865
• add back TWI clock stretching option by @stnolting in #867
• [SLINK] split interrupt into two FIRQs by @stnolting in #868
• B ISA extensions only contains Zba + Zbb + Zbs by @stnolting in #869
• add additional SPI and SDI interrupt conditions by @stnolting in #870

Full Changelog: v1.9.7...v1.9.8

v1.9.7

What's Changed

• [rtl] add generic cache module (not used yet) by @stnolting in #842
• rtl cleanups and optimizations by @stnolting in #843
• ⚠️ remove Wishbone tag signal by @stnolting in #845
• ⚠️⚠️ Rename external bus interface by @stnolting in #846
• ✨ Add optional external bus interface cache (XCACHE) by @stnolting in #849
• ⚠️ processor configuration edits / clean-ups by @stnolting in #850
• Minor cache updates by @stnolting in #851
• [litex] update core complex wrapper by @stnolting in #852
• rework cache system by @stnolting in #853
• Connected SPI bus to on-board Flash and SPI peripheral by @lovelesh-mis in #854
• Update CFU example: use XTEA as "real world" demo application by @stnolting in #855
• Updated Performance test by @mikaelsky in #844

New Contributors

• @lovelesh-mis made their first contribution in #854

Full Changelog: v1.9.6...v1.9.7

v1.9.6

What's Changed

• Allow disabling certain PMP modes by @stnolting in #808
• [revert] remove page faults support by @stnolting in #809
• 🐛 Fix bug in CRT0 trap handler by @stnolting in #812
• ⚠️ Rework hardware performance monitor (HPM) events by @stnolting in #811
• 🧪 [makefile] pass CC_OPTS variable as define string by @stnolting in #813
• ⚠️ remove Smcntrpmf ISA extension by @stnolting in #814
• [sim] add simulation check to sw makefiles as target 'sim-check' by @umarcor in #817
• [SLINK] add AXI-stream-compatible "tlast" signals by @stnolting in #815
• [docs/userguide/simulating_the_processor] add admonition and recommend MARCH=rv32im to build hello_world by @umarcor in #819
• [ci] split SoftwareFrameworkTests from simple testbench simulation by @umarcor in #820
• 🐛 Fix write access to mip.firq CSR bits by @stnolting in #821
• [ci] test example hello_world as well by @umarcor in #822
• [fifo] fix (Vivado) synthesis issue by @stnolting in #827
• optimize FIFO component to improve mapping by @stnolting in #828
• Added dummy clocks for SLINK streams in AXI4-Lite wrapper by @robhancocksed in #831
• 🐛 fix atomic write/clear/set accesses of clear-only CSR bits by @stnolting in #829
• [sw] remove unused variable RISCV_TOOLCHAIN by @umarcor in #832
• 🐛 fix GPTMR threshold = 0 configuration by @stnolting in #834
• Small correction in user guide by @davidgussler in #835

New Contributors

• @robhancocksed made their first contribution in #831
• @davidgussler made their first contribution in #835

Full Changelog: v1.9.5...v1.9.6

v1.9.5

What's Changed

• fix trap priority by @stnolting in #784
• Add support for page fault exceptions by @stnolting in #786
• [cpu] fix minor bug in instruction request bus by @stnolting in #790
• Fix for issue #785: FPU fflags no being asserted correctly by @mikaelsky in #788
• 🐛 [cpu] fix non-stable privilege signal of instruction interface by @stnolting in #792
• [CPU] close further illegal instruction loopholes by @stnolting in #797
• ✨ add optional XIP cache by @stnolting in #799
• add fence signal to CPU bus by @stnolting in #800
• 🐛 fix fence signal pass-through in caches by @stnolting in #802
• [rtl] fix HPM null range assertions by @stnolting in #803
• minor rtl edits by @stnolting in #804
• Fixes to the FPU for issue #791 by @mikaelsky in #794
• 🐛 fix another C-ISA loophole by @stnolting in #806
• Add DMA fence operation by @stnolting in #807

Full Changelog: v1.9.4...v1.9.5

v1.9.4

What's Changed

• [rtl] minor cleanups and optimizations by @stnolting in #764
• [rtl] optimize bus switch by @stnolting in #769
• 🐛 Remove RVC float load/store instructions by @stnolting in #771
• ✨ add optional CPU clock gating by @stnolting in #775
• 🐛 fix typo that renders the clock gating useless by @stnolting in #776
• [rtl] improve CPU front end by @stnolting in #777
• Updated FIFO NULL assertion fix by @mikaelsky in #778
• set top entiy input defaults to 'L' or 'H' by @stnolting in #779
• 🧪 extend switchable clock domain by @stnolting in #780
• Fix for issue #782 by @mikaelsky in #783

Full Changelog: v1.9.3...v1.9.4

v1.9.3

What's Changed

• ✨ Add RISC-V Zicond ISA extension by @stnolting in #743
• [rtl] reset mstatus.mpp to machine-mode by @stnolting in #745
• refine behaviour of CPU sleep signal by @stnolting in #746
• [rtl] minor rtl code cleanups by @stnolting in #747
• [sw] Clean-up software framework by @stnolting in #752
• [rtl] rework FIFO module (to allow inferring block RAM) by @stnolting in #754
• [rtl] minor edits, clean-ups and optimizations; 🔒 set mepc/mtvec/dpc reset value to CPU boot address by @stnolting in #755
• Add GPTMR timer capture by @stnolting in #759
• [rtl] minor code cleanups by @stnolting in #760
• [rtl/core] add again mtime_o to top entity by @mcoroyer in #762
• [rtl] fix minor VHDL coding style issue by @stnolting in #763

New Contributors

• @mcoroyer made their first contribution in #762

Full Changelog: v1.9.2...v1.9.3

v1.9.2

What's Changed

• Fix comment mistake by @Unike267 in #727
• [SPI] re-add high-speed mode by @stnolting in #730
• [XIP] add clock divider for fine-tuning by @stnolting in #731
• 🐛 [FPU] fix wiring of exception flags by @stnolting in #733
• 🐛 fix bug in instruction-misaligned exception handling by @stnolting in #734
• [rtl] cleanup & rework/optimize CPU branch system by @stnolting in #735
• ✨ Add "ASIC style" register file option by @stnolting in #736
• [rtl] Cleanup/update assertions and "auto-configuration" by @stnolting in #738
• Update hardware tigger module (Sdtrig) to version 1.0 by @stnolting in #739
• Add menvcfg[h] CSRs by @stnolting in #741
• [RTE] minor updates by @stnolting in #742

Full Changelog: v1.9.1...v1.9.2