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Add SLINK routing information ports #908

Merged
merged 9 commits into from
May 22, 2024
Merged

Add SLINK routing information ports #908

merged 9 commits into from
May 22, 2024

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stnolting
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@stnolting stnolting commented May 21, 2024

This PR adds two new 4-bit ports to the SLINK module allowing the single RX/TX ports to access up to 16 stream link sources/sinks (via a switch or interconnect).

New top entity ports:

  • slink_rx_src_i, input, 4-bit, compatible to AXI-stream's TID signal
  • slink_tx_dst_o, output, 4-bit, compatible to AXI-stream's TDEST signal

The routing information is also fully buffered by the SLINK's internal RX/TX FIFOs.

@stnolting stnolting added enhancement New feature or request HW hardware-related labels May 21, 2024
@stnolting stnolting self-assigned this May 21, 2024
@stnolting stnolting linked an issue May 21, 2024 that may be closed by this pull request
@stnolting stnolting marked this pull request as ready for review May 21, 2024 20:05
@stnolting stnolting merged commit c5dd617 into main May 22, 2024
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@stnolting stnolting deleted the slink_routing branch May 22, 2024 05:44
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Add AXI stream routing?!
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