✨ Add "ASIC style" register file option

[stnolting]

This PR adds a new "CPU tuning" configuration generic that allows to adapt the architecture style of the CPU's general purpose data register file:

REGFILE_HW_RST : boolean := false;

When REGFILE_HW_RST = false

• default case
• register file is implemented as plain memory array
• will infer block RAM / maps to FPGA memory resources
• no dedicated hardware reset of the register file
• register x0/zero is implemented as physical register that has to be explicitly cleared (done transparently by the CPU control hardware)
• recommended for FPGA designs

When REGFILE_HW_RST = true

• register file is implemented as individual flip flops
  • 31*31=992 FFs for rv32i
  • 15*32=480 FFs for rv32e
• cannot be mapped to FPGA block RAM
• full dedicated hardware reset of the register file
• register x0/zero is hardwired to zero
• recommended for ASIC designs or security-critical setups that require full data erasure on hardware reset