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Add UART FIFO clear flags; add DMA FIRQ interrupt configuration #930

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merged 11 commits into from
Jun 23, 2024

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@stnolting stnolting commented Jun 22, 2024

UART

Add two new control register bits to manually clear the RX / TX FIFOs:

  • bit 28: UART_CTRL_RX_CLR, flag auto-clears
  • bit 29:UART_CTRL_TX_CLR, flag auto-clears

DMA

Add new FIRQ interrupt type configuration flag:

  • bit 15: DMA_CTRL_FIRQ_TYPE
    • when 0: trigger DMA operation on rising-edge of selected FIRQ channel (e.g. trigger only once)
    • when 1: trigger DMA operation whenever the selected FIRQ channel is active/high (e.g. trigger again and again)

@stnolting stnolting added enhancement New feature or request HW hardware-related labels Jun 22, 2024
@stnolting stnolting self-assigned this Jun 22, 2024
@stnolting stnolting marked this pull request as ready for review June 22, 2024 17:26
@stnolting stnolting merged commit f4bcc2f into main Jun 23, 2024
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@stnolting stnolting deleted the dev220624 branch June 23, 2024 07:28
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