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馃悰 Fix write access to mip.firq CSR bits #821

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Feb 21, 2024
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@stnolting stnolting commented Feb 20, 2024

Fixing #818

Write accesses to the mip FIRQ CSR bits always impacted all FIRQ bits (making clearing/acknowledging a single FIRQ impossible). As a side-effect of this fix the mip.firq bits are now read-write. Hence, software can trigger FIRQ manually by writing 1 to the according FIRQ bits.

@stnolting stnolting added bug Something isn't working HW hardware-related labels Feb 20, 2024
@stnolting stnolting self-assigned this Feb 20, 2024
@stnolting stnolting linked an issue Feb 20, 2024 that may be closed by this pull request
@stnolting stnolting marked this pull request as ready for review February 20, 2024 22:50
@stnolting stnolting merged commit d0c3cfa into main Feb 21, 2024
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@stnolting stnolting deleted the fix_mip_firq_access branch February 21, 2024 16:15
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Possible issue with FIRQ pending interrupt clearing
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