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✨ Add RISC-V Zicond ISA extension #743

Merged
merged 11 commits into from
Dec 2, 2023
Merged

✨ Add RISC-V Zicond ISA extension #743

merged 11 commits into from
Dec 2, 2023

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stnolting
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This PR adds support for the recently ratified Zicond ISA extension providing conditional operation primitives. The extension is enabled by a new top generic:

CPU_EXTENSION_RISCV_Zicond : boolean := false;

Surprisingly, it is already supported by our latest GCC toolchain (binutils).

@stnolting stnolting added enhancement New feature or request risc-v compliance Modification to comply with official RISC-V specs. labels Dec 2, 2023
@stnolting stnolting self-assigned this Dec 2, 2023
@stnolting stnolting marked this pull request as ready for review December 2, 2023 07:08
@stnolting stnolting merged commit c303756 into main Dec 2, 2023
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@stnolting stnolting deleted the zicond_isa_ext branch December 2, 2023 10:34
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enhancement New feature or request risc-v compliance Modification to comply with official RISC-V specs.
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