✨ Add RISC-V Zicond ISA extension (#743)

CHANGELOG.md

@@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Link |
 |:----:|:-------:|:--------|:----:|
+| 02.12.2023 | 1.9.2.1 | :sparkles: add RISC-V `Zicond` ISA extension (integer conditional operations) | [#743](https://github.com/stnolting/neorv32/pull/743) |
 | 01.12.2023 | [**:rocket:1.9.2**](https://github.com/stnolting/neorv32/releases/tag/v1.9.2) | **New release** | |
 | 01.12.2023 | 1.9.1.9 | add `menvcfg[h]` CSRs | [#741](https://github.com/stnolting/neorv32/pull/741) |
 | 30.11.2023 | 1.9.1.8 | :sparkles: :bug: upgrade RISC-V hardware trigger module (`Sdtrig` ISA extension) to spec. version v1.0 (fixing several minor bugs) | [#739](https://github.com/stnolting/neorv32/pull/739) |

README.md

@@ -113,8 +113,9 @@ setup according to your needs. Note that all of the following SoC modules are en
 [[`B`](https://stnolting.github.io/neorv32/#_b_isa_extension)]
 [[`U`](https://stnolting.github.io/neorv32/#_u_isa_extension)]
 [[`X`](https://stnolting.github.io/neorv32/#_x_isa_extension)]
-[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_isa_extension)]
 [[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_isa_extension)]
+[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_isa_extension)]
+[[`Zicond`](https://stnolting.github.io/neorv32/#_zicond_isa_extension)]
 [[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_isa_extension)]
 [[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_isa_extension)]
 [[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_isa_extension)]

docs/datasheet/cpu.adoc

@@ -401,36 +401,37 @@ The NEORV32 CPU provides several optional RISC-V and custom ISA extensions. The
 via the according <<_processor_top_entity_generics>>. This chapter gives a brief overview of the different ISA extensions.
 
 .NEORV32 Instruction Set Extensions
-[cols="<2,<6,<2"]
+[cols="<2,<5,<3"]
 [options="header",grid="rows"]
 |=======================
-| Name | Description | Note
-| <<_a_isa_extension,`A`>> | Atomic memory access instructions |
-| <<_b_isa_extension,`B`>> | Bit-manipulation instructions |
-| <<_c_isa_extension,`C`>> | Compressed (16-bit) instructions |
-| <<_e_isa_extension,`E`>> | Embedded CPU extension (reduced register file size) |
-| <<_i_isa_extension,`I`>> | Integer instructions | Base ISA
-| <<_m_isa_extension,`M`>> | Integer multiplication and division instructions |
-| <<_u_isa_extension,`U`>> | Less-privileged _user_ mode extension |
-| <<_x_isa_extension,`X`>> | Platform-specific / NEORV32-specific extension | **Always enabled**
-| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction | **Always enabled**
-| <<_zfinx_isa_extension,`Zfinx`>> | Floating-point instructions using integer registers | `F` alternative
-| <<_zicntr_isa_extension,`Zicntr`>> | Base counters extension |
-| <<_zicsr_isa_extension,`Zicsr`>> | Control and status register access instructions | **Always enabled**
-| <<_zihpm_isa_extension,`Zihpm`>> | Hardware performance monitors extension |
-| <<_zmmul_isa_extension,`Zmmul`>> | Integer multiplication-only instruction | `M` alternative)
-| <<_zcfu_isa_extension,`Zcfu`>> | Custom / user-defined instructions |
-| <<_pmp_isa_extension,`PMP`>> | Physical memory protection extension |
-| <<_smcntrpmf_isa_extension,`Smcntrpmf`>> | Counter privilege mode filtering extension |
-| <<_sdext_isa_extension,`Sdext`>> | External debug support extension | For on-chip debugger
-| <<_sdtrig_isa_extension,`Sdtrig`>> | Trigger module extension | For on-chip debugger
+| Name | Description | <<_processor_top_entity_generics, Enabled by Generic>>
+| <<_a_isa_extension,`A`>> | Atomic memory access instructions | `CPU_EXTENSION_RISCV_A`
+| <<_b_isa_extension,`B`>> | Bit-manipulation instructions | `CPU_EXTENSION_RISCV_B`
+| <<_c_isa_extension,`C`>> | Compressed (16-bit) instructions | `CPU_EXTENSION_RISCV_C`
+| <<_e_isa_extension,`E`>> | Embedded CPU extension (reduced register file size) | `CPU_EXTENSION_RISCV_E`
+| <<_i_isa_extension,`I`>> | Integer base ISA | Enabled if `CPU_EXTENSION_RISCV_E` is **not** enabled
+| <<_m_isa_extension,`M`>> | Integer multiplication and division instructions | `CPU_EXTENSION_RISCV_M`
+| <<_u_isa_extension,`U`>> | Less-privileged _user_ mode extension | `CPU_EXTENSION_RISCV_U`
+| <<_x_isa_extension,`X`>> | Platform-specific / NEORV32-specific extension | Always enabled
+| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction | Always enabled
+| <<_zfinx_isa_extension,`Zfinx`>> | Floating-point instructions using integer registers | `CPU_EXTENSION_RISCV_Zfinx`
+| <<_zicntr_isa_extension,`Zicntr`>> | Base counters extension | `CPU_EXTENSION_RISCV_Zicntr`
+| <<_zicond_isa_extension,`Zicond`>> | Integer conditional operations | `CPU_EXTENSION_RISCV_Zicond` 
+| <<_zicsr_isa_extension,`Zicsr`>> | Control and status register access instructions | Always enabled
+| <<_zihpm_isa_extension,`Zihpm`>> | Hardware performance monitors extension | `CPU_EXTENSION_RISCV_Zihpm`
+| <<_zmmul_isa_extension,`Zmmul`>> | Integer multiplication-only instruction | `CPU_EXTENSION_RISCV_Zmmul`
+| <<_zcfu_isa_extension,`Zcfu`>> | Custom / user-defined instructions | `CPU_EXTENSION_RISCV_Zxcfu`
+| <<_pmp_isa_extension,`PMP`>> | Physical memory protection extension | `PMP_NUM_REGIONS`
+| <<_smcntrpmf_isa_extension,`Smcntrpmf`>> | Counter privilege mode filtering extension | `CPU_EXTENSION_RISCV_U`
+| <<_sdext_isa_extension,`Sdext`>> | External debug support extension | `ON_CHIP_DEBUGGER_EN`
+| <<_sdtrig_isa_extension,`Sdtrig`>> | Trigger module extension | `ON_CHIP_DEBUGGER_EN`
 |=======================
 
 .RISC-V ISA Specifications
 [TIP]
 For more information regarding the RISC-V ISA extensions please refer to the "RISC-V Instruction Set Manual - Volume
-I: Unprivileged ISA" and "The RISC-V Instruction Set Manual Volume II: Privileged Architecture", which are also
-available in the projects `docs/references` folder.
+I: Unprivileged ISA" and "The RISC-V Instruction Set Manual Volume II: Privileged Architecture" Acopy of all currently
+implemented ISA extensions can be found in the projects `docs/references` folder.
 
 .Discovering ISA Extensions
 [TIP]
@@ -494,8 +495,9 @@ to maintain data cache coherency (e.g. by using the `fence` instruction).
 
 ==== `B` ISA Extension
 
-The `B` ISA extension adds instructions for bit-manipulation operations. The NEORV32 `B` ISA extension includes
-the following sub-extensions:
+The `B` ISA extension adds instructions for bit-manipulation operations.
+This ISA extension is implemented as multi-cycle ALU co-process (`rtl/core/neorv32_cpu_cp_bitmanip.vhd`).
+The NEORV32 `B` ISA extension includes the following sub-extensions:
 
 * `Zba` - Address-generation instructions
 * `Zbb` - Basic bit-manipulation instructions
@@ -590,13 +592,15 @@ will raise an illegal instruction exception if the `TW` bit of <<_mstatus>> is s
 
 .Barrel Shifter
 [TIP]
-Shift operations can be accelerated (at the cost of additional logic resources) by enabling the `FAST_SHIFT_EN`
+The shift operations are implemented as multi-cycle ALU co-process (`rtl/core/neorv32_cpu_cp_shifter.vhd`).
+These operations can be accelerated (at the cost of additional logic resources) by enabling the `FAST_SHIFT_EN`
 configuration option that will replace the (time-variant) bit-serial shifter by a (time-constant) barrel shifter.
 
 
 ==== `M` ISA Extension
 
 Hardware-accelerated integer multiplication and division operations are available via the RISC-V `M` ISA extension.
+This ISA extension is implemented as multi-cycle ALU co-process (`rtl/core/neorv32_cpu_cp_muldiv.vhd`).
 
 .Instructions and Timing
 [cols="<2,<4,<3"]
@@ -657,6 +661,7 @@ instead of a dedicated floating-point register file. Thus, the `Zfinx` extension
 less hardware resources and features faster context changes. This also implies that there are NO dedicated `f`
 register file-related load/store or move instructions. The `Zfinx` extension'S floating-point unit is controlled
 via dedicated <<_floating_point_csrs>>.
+This ISA extension is implemented as multi-cycle ALU co-process (`rtl/core/neorv32_cpu_cp_fpu.vhd`).
 
 .Fused Multiply-Add and Division Instructions
 [WARNING]
@@ -697,6 +702,21 @@ This extensions is stated as _mandatory_ by the RISC-V spec. However, area-const
 support for these counters. 
 
 
+==== `Zicond` ISA Extension
+
+The `Zicond` ISA extension adds integer conditional move primitives that allow to implement branch-less
+control flows. It is enabled by the top's `CPU_EXTENSION_RISCV_Zicond` generic.
+This ISA extension is implemented as multi-cycle ALU co-process (`rtl/core/neorv32_cpu_cp_cond.vhd`).
+
+.Instructions and Timing
+[cols="<2,<4,<3"]
+[options="header", grid="rows"]
+|=======================
+| Class | Instructions | Execution cycles
+| Conditional | `czero.eqz` `czero.nez` | 3
+|=======================
+
+
 ==== `Zicsr` ISA Extension
 
 This ISA extensions provides instructions for accessing the <<_control_and_status_registers_csrs>> as well as further

docs/datasheet/cpu_csr.adoc

@@ -1032,7 +1032,7 @@ discover ISA sub-extensions and CPU configuration options
 |  3    | `CSR_MXISA_ZXCFU`     | r/- | <<_zxcfu_isa_extension>> available
 |  4    | `CSR_MXISA_SMCNTRPMF` | r/- | <<_smcntrpmf_isa_extension>> available
 |  5    | `CSR_MXISA_ZFINX`     | r/- | <<_zfinx_isa_extension>> available
-|  6    | -                     | r/- | hardwired to zero
+|  6    | `CSR_MXISA_ZICOND`    | r/- | <<_zicond_isa_extension>> available
 |  7    | `CSR_MXISA_ZICNTR`    | r/- | <<_zicntr_isa_extension>> available
 |  8    | `CSR_MXISA_PMP`       | r/- | <<_pmp_isa_extension>> available
 |  9    | `CSR_MXISA_ZIHPM`     | r/- | <<_zihpm_isa_extension>> available

docs/datasheet/overview.adoc

@@ -178,63 +178,65 @@ The list below shows the hierarchical compile order srarting at the top.
 
 .VHDL Library
 [IMPORTANT]
-All core VHDL files from the list below have to be assigned to a new design library named `neorv32`.
+All core VHDL files from the list below have to be assigned to a **new library** named `neorv32`.
 
 ...................................
-
 ┌-neorv32_package.vhd              - Processor/CPU main VHDL package file
 ├-neorv32_fifo.vhd                 - Generic FIFO component
 │
 │   ┌-neorv32_cpu_cp_bitmanip.vhd  - Bit-manipulation co-processor (B ext.)
 │   ├-neorv32_cpu_cp_cfu.vhd       - Custom instructions co-processor (Zxcfu ext.)
+│   ├-neorv32_cpu_cp_cond.vhd      - Integer conditional operations (Zicond ext.)
 │   ├-neorv32_cpu_cp_fpu.vhd       - Floating-point co-processor (Zfinx ext.)
 │   ├-neorv32_cpu_cp_shifter.vhd   - Bit-shift co-processor (base ISA)
 │   ├-neorv32_cpu_cp_muldiv.vhd    - Mul/Div co-processor (M ext.)
+│   │
 │ ┌-neorv32_cpu_alu.vhd            - Arithmetic/logic unit
-│ ├-neorv32_cpu_pmp.vhd            - Physical memory protection unit
+│ ├-neorv32_cpu_pmp.vhd            - Physical memory protection unit (Smpmp ext.)
 │ ├-neorv32_cpu_lsu.vhd            - Load/store unit
-│ │ ┌-neorv32_cpu_decompressor.vhd - Compressed instructions decoder
+│ │ ┌-neorv32_cpu_decompressor.vhd - Compressed instructions decoder (C ext.)
 │ ├-neorv32_cpu_control.vhd        - CPU control, exception system and CSRs
 │ ├-neorv32_cpu_regfile.vhd        - Data register file
-├-neorv32_cpu.vhd                  - NEORV32 CPU top entity
+│ │
+├-neorv32_cpu.vhd                  - NEORV32 CPU TOP ENTITY
 │
-├-mem/neorv32_dmem.default.vhd     - _Default_ data memory (architecture-only)
-├-mem/neorv32_imem.default.vhd     - _Default_ instruction memory (architecture-only)
+├-mem/neorv32_dmem.default.vhd     - *Default* data memory (architecture-only)
+├-mem/neorv32_imem.default.vhd     - *Default* instruction memory (architecture-only)
 │
 │ ┌-neorv32_bootloader_image.vhd   - Bootloader ROM memory image
 ├-neorv32_boot_rom.vhd             - Bootloader ROM
 │
 │ ┌-neor32_application_image.vhd   - IMEM application initialization image
 ├-neorv32_imem.entity.vhd          - Processor-internal instruction memory (entity-only!)
 │
-├neorv32_cfs.vhd                   - Custom functions subsystem
-├neorv32_crc.vhd                   - Cyclic redundancy check unit
-├neorv32_dcache.vhd                - Processor-internal data cache
-├neorv32_debug_dm.vhd              - on-chip debugger: debug module
-├neorv32_debug_dtm.vhd             - on-chip debugger: debug transfer module
-├neorv32_dma.vhd                   - Direct memory access controller
-├neorv32_dmem.entity.vhd           - Processor-internal data memory (entity-only!)
-├neorv32_gpio.vhd                  - General purpose input/output port unit
-├neorv32_gptmr.vhd                 - General purpose 32-bit timer
-├neorv32_icache.vhd                - Processor-internal instruction cache
-├neorv32_intercon.vhd              - SoC bus infrastructure
-├neorv32_mtime.vhd                 - Machine system timer
-├neorv32_neoled.vhd                - NeoPixel (TM) compatible smart LED interface
-├neorv32_onewire.vhd               - One-Wire serial interface controller
-├neorv32_pwm.vhd                   - Pulse-width modulation controller
-├neorv32_sdi.vhd                   - Serial data interface controller (SPI device)
-├neorv32_slink.vhd                 - Stream link interface
-├neorv32_spi.vhd                   - Serial peripheral interface controller (SPI host)
-├neorv32_sysinfo.vhd               - System configuration information memory
-├neorv32_trng.vhd                  - True random number generator
-├neorv32_twi.vhd                   - Two wire serial interface controller
-├neorv32_uart.vhd                  - Universal async. receiver/transmitter
-├neorv32_wdt.vhd                   - Watchdog timer
-├neorv32_wishbone.vhd              - External (Wishbone) bus interface
-├neorv32_xip.vhd                   - Execute in place module
-├neorv32_xirq.vhd                  - External interrupt controller
+├-neorv32_cfs.vhd                  - Custom functions subsystem
+├-neorv32_crc.vhd                  - Cyclic redundancy check unit
+├-neorv32_dcache.vhd               - Processor-internal data cache
+├-neorv32_debug_dm.vhd             - on-chip debugger: debug module
+├-neorv32_debug_dtm.vhd            - on-chip debugger: debug transfer module
+├-neorv32_dma.vhd                  - Direct memory access controller
+├-neorv32_dmem.entity.vhd          - Processor-internal data memory (entity-only!)
+├-neorv32_gpio.vhd                 - General purpose input/output port unit
+├-neorv32_gptmr.vhd                - General purpose 32-bit timer
+├-neorv32_icache.vhd               - Processor-internal instruction cache
+├-neorv32_intercon.vhd             - SoC bus infrastructure
+├-neorv32_mtime.vhd                - Machine system timer
+├-neorv32_neoled.vhd               - NeoPixel (TM) compatible smart LED interface
+├-neorv32_onewire.vhd              - One-Wire serial interface controller
+├-neorv32_pwm.vhd                  - Pulse-width modulation controller
+├-neorv32_sdi.vhd                  - Serial data interface controller (SPI device)
+├-neorv32_slink.vhd                - Stream link interface
+├-neorv32_spi.vhd                  - Serial peripheral interface controller (SPI host)
+├-neorv32_sysinfo.vhd              - System configuration information memory
+├-neorv32_trng.vhd                 - True random number generator
+├-neorv32_twi.vhd                  - Two wire serial interface controller
+├-neorv32_uart.vhd                 - Universal async. receiver/transmitter
+├-neorv32_wdt.vhd                  - Watchdog timer
+├-neorv32_wishbone.vhd             - External (Wishbone) bus interface
+├-neorv32_xip.vhd                  - Execute in place module
+├-neorv32_xirq.vhd                 - External interrupt controller
 │
-neorv32_top.vhd                    - NEORV32 Processor top entity
+neorv32_top.vhd                    - NEORV32 PROCESSOR TOP ENTITY
 ...................................
 
 [NOTE]

docs/datasheet/soc.adoc

@@ -210,6 +210,7 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 | `CPU_EXTENSION_RISCV_U`      | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode).
 | `CPU_EXTENSION_RISCV_Zfinx`  | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit).
 | `CPU_EXTENSION_RISCV_Zicntr` | boolean | true  | Enable <<_zicntr_isa_extension>> (CPU base counters).
+| `CPU_EXTENSION_RISCV_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional operations).
 | `CPU_EXTENSION_RISCV_Zihpm`  | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors).
 | `CPU_EXTENSION_RISCV_Zmmul`  | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
 | `CPU_EXTENSION_RISCV_Zxcfu`  | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).