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✨ Add RISC-V Zicond ISA extension #743

Merged
merged 11 commits into from
Dec 2, 2023
Merged

✨ Add RISC-V Zicond ISA extension #743

merged 11 commits into from
Dec 2, 2023

Commits on Dec 1, 2023

  1. [sw/lib] add Zicond MXISA bit

    @stnolting
    stnolting committed Dec 1, 2023
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  2. [docs/references] add Zicond spec

    @stnolting
    stnolting committed Dec 1, 2023
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  3. [rtl] add Zicond co-processor VHDL source

    @stnolting
    stnolting committed Dec 1, 2023
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Commits on Dec 2, 2023

  1. [rtl] add cp5 (cond)

    @stnolting
    stnolting committed Dec 2, 2023
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  2. [top] add new top generic to enable Zicond 

    CPU_EXTENSION_RISCV_Zicond
    @stnolting
    stnolting committed Dec 2, 2023
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  3. [cpu] add Zicond instructions to back-end

    @stnolting
    stnolting committed Dec 2, 2023
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  4. [sim] enable Zicond in testbenches

    @stnolting
    stnolting committed Dec 2, 2023
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  5. [changelog] add v1.9.2.1

    @stnolting
    stnolting committed Dec 2, 2023
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  6. [docs] update ISA sections, add Zicond

    @stnolting
    stnolting committed Dec 2, 2023
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  7. [README] add Zicond

    @stnolting
    stnolting committed Dec 2, 2023
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  8. [figures] processor: add Zicond ISA block

    @stnolting
    stnolting committed Dec 2, 2023
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