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[rtl] add generic cache module (not used yet) #842

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merged 11 commits into from
Mar 9, 2024
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This PR adds a new generic cache module that will might replace the I- and D-cache modules. Right now, this new cache module is not used at all by the default processor setup.

Cache specs:

  • direct-mapped, configurable block size ("cache lines"), configurable number of blocks
  • write-back strategy: write back dirty cache blocks when the block is replaced
  • write-allocate: a write miss will load the entire block from memory
  • supports direct (uncached) memory accesses

⚠️ work in progress (but synthesis and simulation looks good)
the sim target can be used to simulate "any" configuration (when the default testbench is adjusted) and maybe APP_IMG is not used at all
they take too much time (clearing the caches); fence[.i] instructions are tested implicitly by other test cases
- no fence request via direct access port
- add UC_ENABLE to enable/disable direct/uncached accesses
can cause unresolvable aliasing
@stnolting stnolting added HW hardware-related optimization Make things faster, smaller and more efficient labels Mar 9, 2024
@stnolting stnolting self-assigned this Mar 9, 2024
@stnolting stnolting marked this pull request as ready for review March 9, 2024 06:58
@stnolting stnolting merged commit a2bc846 into main Mar 9, 2024
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@stnolting stnolting deleted the generic_cache branch March 9, 2024 09:16
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