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[rtl] add generic cache module (not used yet) #842

Merged
merged 11 commits into from
Mar 9, 2024
Merged

[rtl] add generic cache module (not used yet) #842

merged 11 commits into from
Mar 9, 2024

Commits on Mar 4, 2024

  1. [rtl] add new generic cache module 

    ⚠️ work in progress (but synthesis and simulation looks good)
    @stnolting
    stnolting committed Mar 4, 2024
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  2. [docs] add note: adding internal bus pipeline stages

    @stnolting
    stnolting committed Mar 4, 2024
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  3. [makefile] fix sim target message 

    the sim target can be used to simulate "any" configuration (when the default testbench is adjusted) and maybe APP_IMG is not used at all
    @stnolting
    stnolting committed Mar 4, 2024
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  4. [processor_check] remove fence test cases 

    they take too much time (clearing the caches); fence[.i] instructions are tested implicitly by other test cases
    @stnolting
    stnolting committed Mar 4, 2024
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Commits on Mar 6, 2024

  1. [cache] minor edits 

    - no fence request via direct access port
- add UC_ENABLE to enable/disable direct/uncached accesses
    @stnolting
    stnolting committed Mar 6, 2024
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Commits on Mar 8, 2024

  1. [cache] clean-ups

    @stnolting
    stnolting committed Mar 8, 2024
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  2. [cache] minor fixes and optimizations

    @stnolting
    stnolting committed Mar 8, 2024
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  3. [cache] remove VSPLIT option 

    can cause unresolvable aliasing
    @stnolting
    stnolting committed Mar 8, 2024
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  4. [cache] further cleanups

    @stnolting
    stnolting committed Mar 8, 2024
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Commits on Mar 9, 2024

  1. [processor_check] attribute cleanups

    @stnolting
    stnolting committed Mar 9, 2024
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  2. add v1.9.6.1

    @stnolting
    stnolting committed Mar 9, 2024
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