v1.9.2
What's Changed
- Fix comment mistake by @Unike267 in #727
- [SPI] re-add high-speed mode by @stnolting in #730
- [XIP] add clock divider for fine-tuning by @stnolting in #731
- 🐛 [FPU] fix wiring of exception flags by @stnolting in #733
- 🐛 fix bug in instruction-misaligned exception handling by @stnolting in #734
- [rtl] cleanup & rework/optimize CPU branch system by @stnolting in #735
- ✨ Add "ASIC style" register file option by @stnolting in #736
- [rtl] Cleanup/update assertions and "auto-configuration" by @stnolting in #738
- Update hardware tigger module (Sdtrig) to version 1.0 by @stnolting in #739
- Add menvcfg[h] CSRs by @stnolting in #741
- [RTE] minor updates by @stnolting in #742
Full Changelog: v1.9.1...v1.9.2