Update hardware tigger module (Sdtrig) to version 1.0

[stnolting]

This PR upgrades the CPU's hardware trigger module (Sdtrig ISA extension) to v1.0 and also fixes some bugs present in the previous version.

• upgrade Sdtrig from version 0.13 to version 1.0
• replace mcontrol trigger (deprecated) by mcontrol6 trigger
• fix invalid write access to tdata* CSRs when dmode is set an CPU is not in debug-mode
• fix "timing" of hardware trigger match
  • the trigger module now generates a breakpoint exception / enter debug-mode when execution reaches the programmed address but before actually executing the instruction at that address
  • i.e. mepc/dpc will point to the next instruction that has to be executed (after returning from exception / after returning from debug-mode) to preserve program flow