v1.9.3

What's Changed

• ✨ Add RISC-V Zicond ISA extension by @stnolting in #743
• [rtl] reset mstatus.mpp to machine-mode by @stnolting in #745
• refine behaviour of CPU sleep signal by @stnolting in #746
• [rtl] minor rtl code cleanups by @stnolting in #747
• [sw] Clean-up software framework by @stnolting in #752
• [rtl] rework FIFO module (to allow inferring block RAM) by @stnolting in #754
• [rtl] minor edits, clean-ups and optimizations; 🔒 set mepc/mtvec/dpc reset value to CPU boot address by @stnolting in #755
• Add GPTMR timer capture by @stnolting in #759
• [rtl] minor code cleanups by @stnolting in #760
• [rtl/core] add again mtime_o to top entity by @mcoroyer in #762
• [rtl] fix minor VHDL coding style issue by @stnolting in #763

New Contributors

• @mcoroyer made their first contribution in #762

Full Changelog: v1.9.2...v1.9.3