Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

CPU RTL optimization #857

Merged
merged 7 commits into from
Mar 23, 2024
Merged

CPU RTL optimization #857

merged 7 commits into from
Mar 23, 2024

Conversation

stnolting
Copy link
Owner

  • made interconnect's gateway more generic (in case someone wants to use it for building custom bus systems)
  • optimize CPU data path
    • smaller hardware footprint (~5% smaller)
    • shortened critical path (134MHz, CPU-only, Cyclone 4)

@stnolting stnolting added HW hardware-related optimization Make things faster, smaller and more efficient labels Mar 22, 2024
@stnolting stnolting self-assigned this Mar 22, 2024
@stnolting stnolting marked this pull request as ready for review March 22, 2024 21:17
@stnolting stnolting merged commit 1fd901c into main Mar 23, 2024
10 checks passed
@stnolting stnolting deleted the dev220324 branch March 23, 2024 10:15
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
HW hardware-related optimization Make things faster, smaller and more efficient
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

1 participant