Release v1.5.7 · stnolting/neorv32

This list shows the main changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

fixed bug in instruction cache flush/re-sync logic (via fence.i instruction) - cache might have missed a re-sync request in some cases
fixed bug in debugger park loop: instruction cache re-sync (fence.i) was missing - caused debugger to execute obsolete code from program buffer

fixed endiannes inconsistencies: processor/CPU is little-endian
⚠️ removed TINY_SHIFT_EN generic; CPU shifter is implemented as iterative single-bit shift by default
⚠️ reworked boot configuration
- removed MEM_INT_IMEM_ROM generic; processor-internal IMEM is implemented as ROM if internal IMEM is enabled (MEM_INT_IMEM_EN = true) and internal bootloader is disabled (INT_BOOTLOADER_EN = false)
⚠️ removed option to grant user-level access to HPM counters (removed according mcounteren CSR bits)
increased processor-internal IO size (from 256 bytes to 512 bytes)
- relocated base address of CFS module
number of PWM channels is now configured via IO_PWM_NUM_CH generic (0=none at all, max 60)
⚠️ CPU B extension has been (temporarily) removed from the core
CPU_CNT_WIDTH and HPM_CNT_WIDTH generics can now also be zero to exclude CPU core counters (cycle & instret) and HPM counters
minor logic optimizations to reduce area requirements and switching activity and to shorten critical path

Merged pull requests:

#47 Update CI to use VUnit for running VHDL testbenches
#48 Introduce VUnit logging and checking
#53 docs: split User Guide
#54 [ci] cleanup
#59 Add examples
#60 [docs] add attrs.adoc and attrs.main.adoc
#61 Reorganise setups
#63 Add Fomu
#64 [sim] split UART logging component, make self-checking
#65 Add VUnit
#66 [sim/VUnit] support CLI argument for selecting the expected UART responses
#67 rename logical library 'iCE40UP' to 'iCE40'
#69 VUnit checking
#71 Add MSYS2 jobs to continuous integration workflows
#72 [ci/riscv-arch-test] make test script executable
#73 [sim] make ghdl_sim.sh executable
#74 [ci/generate-job-matrix] fix UPduino_v3 artifact (bitstream) extension
#75 iCESugar
#76 [setups/examples] add iCESugar Minimal
#79 add mailmap
#80 Added option to print a selected subset of information from processor…
#82 [sim] use custom VUnit loggers for better verbosity control
#83 [setups/osflow] support optionally using Verilog sources and add Fomu MixedLanguage example
#84 [setups/osflow/iCESugar] update PCF

Closed issues:

reworked data sheet section Address Space
- added section Memory Configuration
- added section Boot Configuration
reworked and updated complete User Guide
typo and layout fixes