v1.8.0

What's Changed

• Remove signal initalizations by @tmeissner in #464
• Upgrade on-chip-debugger by @stnolting in #463
• ⚠️ rework CPU debug spec ISA configuration; ✨ enhance trigger module by @stnolting in #465
• [sw] rename library functions by @stnolting in #467
• [rtl] OCD: update DTM and DM by @stnolting in #468
• Fix value of SYSINFO_SOC_IO_ONEWIRE in NEORV32_SYSINFO_SOC_enum by @tmeissner in #469
• [rtl] CPU: logic optimization by @stnolting in #470
• [sw/example/demo_spi_irq]: make read/write data pointer and busy flag… by @akaeba in #471
• [rtl] update TRNG by @stnolting in #472
• [rtl/test_setups] add on-chip debugger test setup by @stnolting in #473
• ⚠️ rework watchdog timer (WDT) by @stnolting in #474
• [rtl] VHDL cleanups by @stnolting in #476
• ⚠️ Rework CPU counters by @stnolting in #477
• [sw] cleanup and update software framework by @stnolting in #478

Full Changelog: v1.7.9...v1.8.0