Remove signal initalizations

[tmeissner]

Initialization of registers via bitstream isn't compatible with at least two FPGA architectures:

• Gatemate FPGA -> leads to an error during systhesis with Yosys
• Microchip SmartFusion & Polarfire FPGAs / SoCs -> init value ignored during synthesis

Both aren't nice, the 2nd one can lead to nasty misbehavior if you rely on the initialization value.

There are two signals with init values in the neorv32 design:

neorv32_top.vhd:  signal rstn_ext_sreg : std_ulogic_vector(3 downto 0) := (others => '0'); -- initialize (reset) via bitstream
neorv32_top.vhd:  signal rstn_int_sreg : std_ulogic_vector(3 downto 0)  := (others => '0'); -- initialize (reset) via bitstream

I propose to remove the initialization resulting in this:

neorv32_top.vhd:  signal rstn_ext_sreg : std_ulogic_vector(3 downto 0);
neorv32_top.vhd:  signal rstn_int_sreg : std_ulogic_vector(3 downto 0);