⚠️ rework CPU debug spec ISA configuration; ✨ enhance trigger module #465
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To fine-configure the debug-mode extensions
stnolting
added
enhancement
* add explicit generics for "Sdext" and "Sdtrig" ISA extension * make trigger module available for m-mode software * provide more configuration options for the trigger module
When in debug-mode all PMP rules are ignored making the debugger have maximum access rights.
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CPU_EXTENSION_RISCV_DEBUGgeneric, which is replaced by two new generics to allow a finer configuration of the available debug spec. ISA extensions:CPU_EXTENSION_RISCV_Sdext: set true to enable the RISC-VSdextISA extension (external debug support, required for the on-chip debugger)CPU_EXTENSION_RISCV_Sdtrig: set true to enable the RISC-VSdtrigISA extension (trigger module)✨ This PR also enhances the capabilities of the RISC-V trigger module (
SdtrigISA extension), which can now also be used independently of the on-chip debugger. The trigger module can raise a machine-mode breakpoint exception when execution reaches a programmable address. A simple example program will be added tosw/example/demo_trigger_module.