v1.6.6

What's Changed

• Fix compile error with questa, for issue #242 by @tmeissner in #243
• ⚠️ Make PWM and XIRQ IOs fixed-sized by @stnolting in #241
• ✨ Add Execute In Place (XIP) Module by @stnolting in #244
• [rtl/core/mem] Rename legacy-style memory files by @stnolting in #246
• [.github/riscv-arch-test] Fix / rework by @stnolting in #248
• [BUSKEEPER] Add NULL address check option by @stnolting in #247
• ⚠️ [XIP] reworked execute in place module by @stnolting in #249
• [SPI & XIP] add high-speed SPI mode option by @stnolting in #251
• setups/osflow/synthesis: recent versions of yosys need command 'read_verilog' by @umarcor in #252
• 🐛 [BUSKEEPER] fix bug in error flag logic by @stnolting in #253
• [GPIO] raise bus exception if writing to INPUT registers by @stnolting in #255

Full Changelog: v1.6.5...v1.6.6