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[.github/riscv-arch-test] Fix / rework #248

Merged
merged 7 commits into from
Jan 5, 2022
Merged

[.github/riscv-arch-test] Fix / rework #248

merged 7 commits into from
Jan 5, 2022

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@stnolting stnolting commented Jan 4, 2022 •
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This PR makes some minor reworks of the riscv-arch-test GitHub actions workflow:

  • use sim package (mainly for RISC-V GCC and GHDL)
  • add status note to sim-only IMEM (ROM)
  • remove rtl/core/mem/*.legacy.vhd files for simulation
  • skip I/jmp-01 test case - the GHDL version used for the architecture tests does not proceed here somehow (using a constant array with more than 400000 elements) - I will further investigate on this...

@stnolting stnolting added the CI Continuous integration-related label Jan 4, 2022
@stnolting stnolting self-assigned this Jan 4, 2022
@stnolting stnolting marked this pull request as ready for review January 4, 2022 16:22
@stnolting stnolting changed the title [.github/riscv-arch-test] Minor rework [.github/riscv-arch-test] Fix / rework Jan 4, 2022
@stnolting stnolting merged commit ef810df into master Jan 5, 2022
@stnolting stnolting deleted the riscv_arch_test_rework branch January 5, 2022 04:24
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