Skip to content

v1.6.4

Compare
Choose a tag to compare
@stnolting stnolting released this 26 Nov 05:35

DOI

Bug Fixes

  • fixed bug in WISHBONE interface: pipelined Wishbone mode did not clear STB after first transfer cycle
  • on-chip debugger: reworked JTAG signal input/output synchronization logic (#216) - JTAG signals were not correctly sampled at the right rising/falling clock edges

Updates and New Features

  • reworked TRNG (#212)
  • ⚠️ removed WI_CTRL_CKSTEN flag (enable clock stretching) from control registers, clock-stretching is now always enabled
  • major control unit and AKU logic optimizations; 🔒 closed further illegal instruction encoding holes (system environment instructions, ALU and ALU-immediate instructions, FENCE instructions) (#204)
  • ⚠️ reworked IRQ trigger logic of SPI, TWI, UART0, UART1, NELOED and SLINK; FIRQs now only trigger once when the programmed interrupt condition is met instead of triggering all the time (#202)
  • added new peripheral module - General Purpose 32-bit Timer GPTMR (#195)

What's Changed

New Contributors

Full Changelog: v1.6.3...v1.6.4