Rework peripheral's FIRQ triggering #202
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+ minor code clean-up
removed CSR access check test case
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This PR changes the behavior of the IO module's fast interrupt request signals.
Affected peripheral devices:
SPI,TWI,UART0,UART1,NEOLED,SLINKPre-PR
In the current pre-PR design the interrupts are triggered whenever the according module is in the interrupt triggering state. For example, the SPI unit's interrupt gets pending whenever the SPI module is idle. This is disruptive because once the interrupt is configured and enabled it keeps firing all the time even if there is no data to be send via SPI right now.
In the current version an interrupt is acknowledged (= no longer pending) by resolving the interrupt-causing conditions. In term of the SPI module this mean triggering a new transmission.
Post-PR
This PR changes the triggering of the module's FIRQ interrupts so that they are triggered when the according module enters the interrupt-triggering state. For example, the SPI unit's interrupt only gets pending once (= only fires once) when the module finishes it's current transmission and enters idle mode. Once the interrupt is processed there will be no new interrupt request until the SPI module finishes another transmission.
This PR also reworks (⚠️ ) the mechanism for acknowledging interrupts. In the updated design interrupt are acknowledged by either writing to a unit' control register (this can also be a dummy write like reading the control register and writing it back) or by reading/writing the module's data register(s) - the last point is device specific.
Example 1: the SPI interrupt is acknowledged by writing the SPI control register or by reading or writing the SPI data register.
Example 2: the UART0 RX interrupt is acknowledged by writing the UART0 control register or by reading the UART0 data register.
Example 3: the UART TX interrupt is acknowledged by writing the UART0 control register or by writing the UART0 data register.
Misc
This PR also reworks the SLINK interrupt system (also the trigger logic) and fixes some bugs in the interrupt logic (also fixing #199).
Waht do you think? 👍? 👎?
Feedback and thoughts are highly appreciated! 😉