[On-Chip Debugger] Fix JTAG timing #216
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The J-Link EDU now works with the new PR up to its maximum frequency of 15MHz. |
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Great to hear! Thanks for the feedback! 👍 |
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This PR reworks the JTAG signal synchronization logic of the DTM (debug transfer module). The pre-PR version of the DTM did not fully comply with the JTAG interface timing requirements (sample TDO and TMS on the rising edge of TCK, update TDO on the falling edge of TCK).
This seems to cause some compatibility troubles with the JLINK EDU as reported by @emb4fun. It would be great if you could test the reworked DTM 😉
This PR also includes some code clean-ups of the DTM code and also removes the number of recommended debugger wait states to allow faster JTAG operations.