v1.6.3

Bug Fixes

• fixed bug in *_reduce_f VHDL functions (#186)
• fixed imprecise illegal instructions exception (ALU-class operations); mepc and mtval did not present the correct exception-causing data

Updates and New Features

• ⚠️ removed CPU_EXTENSION_RISCV_Zbb, added CPU_EXTENSION_RISCV_B generic (#190)
  • all currently supported bit-manipulation sub-extensions are enabled/disabled by the CPU_EXTENSION_RISCV_B generic
  • added support of Zba (address computation instructions) bit-manipulation sub-extension
• added generics to explicitly enable Zicntr and Zihpm extensions (#192)
  • CPU_EXTENSION_RISCV_Zicntr, true by default, implements basic CPU counter CSRs ([m]time, [m]cycle[h], [m]instret[h])
  • CPU_EXTENSION_RISCV_Zihpm, false by default, implements hardware performance monitor CSRs
• added memory-mapped register to BUSKEEPER to identify precise cause of bus access exceptions (#191)
• bootloader now uses physical memory configuration (from SYSINFO) module to setup stack pointer
• added option to configure clock polarity and clock phase of SPI module (#185)
• minor logic optimizations (reducing area footprint and shortening critical path) and code clean-ups

What's Changed

• [SPI] Add CPOL (clock polarity) configuration option by @stnolting in #185
• fix: reduce_f won't work with single bit operands by @gottschalkm in #186
• [setups/ULX3S] increase memory sizes to "default" by @stnolting in #188
• [B ISA Extension] Rework and addition of Zba subset by @stnolting in #190
• [BUSKEEPER] add memory-mapped status register by @stnolting in #191
• RISC-V "Zicntr" and "Zihpm" extensions by @stnolting in #192

Closed Issues

• #140 Usage of Logic Elements almost double when synthesizing for Max 10
• #145 Radiant setup fails to build with Radiant 2.2.1.239.2
• #169 SDRAM controller for the ULX3S
• #181 neorv32/docs/userguide/content.adoc en dash / em dash

New Contributors

• @gottschalkm made their first contribution in #186

Full Changelog: v1.6.2...v1.6.3