[SPI] Add CPOL (clock polarity) configuration option #185
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source: https://en.wikipedia.org/wiki/File:SPI_timing_diagram2.svg ©️ license: * Creative Commons: https://en.wikipedia.org/wiki/Creative_Commons * Attribution-Share Alike 3.0 Unported: https://creativecommons.org/licenses/by-sa/3.0/deed.en
due to updated SPI setup function
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This PR adds a new flag to the SPI module's control register to configure the clock polarity. Together with the clock phase configuration bit, the SPI module now supports all SPI clock modes (0,1,2,3).
This PR is also a makeover of the SPI's VHDL source code (clean-up and logic optimization).
✔️ The changes made by this PR are fully backwards-compatible (except for the provided C-language
neorv32_spi_setupfunction prototype, which now requires an additional argument).