[B ISA Extension] Rework and addition of Zba subset

[stnolting]

This PR is a rework of the NEOR32 preliminary support of the RISC-V bit-manipulation ISA extension B. It adds the address generation instructions subset Zba to the already implemented basic bit-manipulation instructions subset Zbb.

This PR also reworks the configuration generic of the bit-manipulation extensions:

• the CPU_EXTENSION_RISCV_Zbb top generic is removed
  • the SYSINFO_CPU_ZBB flag from the SYSINFO module is removed
• the CPU_EXTENSION_RISCV_B top generic is added and will implement all currently support subsets (Zba Zbb) when "true"
  • software can now determine if the NEORV32 B extensions is implemented by checking the according misa CSR bit

⚠️ Note that the RISC-V B extension is frozen but not officially ratified yet. Hence, there is no upstream gcc support available at this time. However, the NEORV32 B extension can still be utilized via the provided intrinsics (sw/example/bitmanip_test/neorv32_b_extension_intrinsics.h).

⚠️ RISC-V Compatibility: The RISC-V spec states that all Zb* subsets have to be implemented when the B bit in the misa CSR is set. This is a NEORV32-specific deviation from the spec.

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I accidentally added minor VHDL source code clean-ups of the TWI module to this PR. I won't revert that commit because it is entirely cosmetic 😉