v1.6.0

This list shows the main core changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• fixed bug in mret instruction (caused an exception if user mode was not implemented)
• fixed missing flash_sdi_i in Radiant-related example setups and processor wrappers

💡 Updates and New Features

• ⚠️ removed USER_CODE generic and according SYSINFO register
• ⚠️ removed custom mzext CSR; moved all information flags to new SYSINFO_CPU register in SYSINFO module
• ⚠️ removed mstatus.SD and mstatus.FS CSR flags
• added new designated test setups: rtl/test_setups, 📚 UG: General Hardware Setup
• fixed Zifencei test of riscv-arch-test port
• added flags to SYSINFO module to check FAST_SHIFT_EN and FAST_MUL_EN generics by software
• ✨ added support for RISC-V Zbb extension (basic bit-manipulation operations); support via intrinsic library

✔️ Pull Requests and Issues

Merged pull requests:

• #136 [proposal] add rtl/test_setups
• #137 Move osflow examples
• #139 Added AlhambraII and ULX3S boards
• #142 split rtl/templates folder
• #143 SYSINFO documentation fixups
• #144 [setups] add terasic cyclone v starter kit
• #149 [setup/osflow/boards/index.mk] do not set GHDL_PLUGIN_MODULE unconditionally

Closed issues:

• #128 Do we really need wrappers for the top entity?
• #132 Cannot fit on XC6SLX9
• #135 Missing documentation and Makefiles for iCE40 and ECP5 Lattice FPGAs
• #138 common/common.mk : 144 main.elf Error 1
• #148 Windows workflow keeps failing