Added AlhambraII and ULX3S boards #139

zipotron · 2021-08-09T18:51:07Z

Alhambra failing in the design, maybe optimization, ULX3S Failing for some misconfiguration in Makefiles.
I need help with ULX3S, I got this error:
ghdl -a --std=08 --work=ecp5 devices/ecp5/ecp5_components.vhd ghdl -a --std=08 --work=neorv32 ../../rtl/core/neorv32_package.vhd ../../rtl/core/neorv32_application_image.vhd devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd ../../rtl/core/neorv32_bootloader_image.vhd ../../rtl/core/neorv32_boot_rom.vhd ../../rtl/core/neorv32_bus_keeper.vhd ../../rtl/core/neorv32_busswitch.vhd ../../rtl/core/neorv32_cfs.vhd ../../rtl/core/neorv32_cpu.vhd ../../rtl/core/neorv32_cpu_alu.vhd ../../rtl/core/neorv32_cpu_bus.vhd ../../rtl/core/neorv32_cpu_control.vhd ../../rtl/core/neorv32_cpu_cp_fpu.vhd ../../rtl/core/neorv32_cpu_cp_muldiv.vhd ../../rtl/core/neorv32_cpu_cp_shifter.vhd ../../rtl/core/neorv32_cpu_decompressor.vhd ../../rtl/core/neorv32_cpu_regfile.vhd ../../rtl/core/neorv32_debug_dm.vhd ../../rtl/core/neorv32_debug_dtm.vhd ../../rtl/core/neorv32_fifo.vhd ../../rtl/core/neorv32_gpio.vhd ../../rtl/core/neorv32_icache.vhd ../../rtl/core/neorv32_mtime.vhd ../../rtl/core/neorv32_neoled.vhd ../../rtl/core/neorv32_pwm.vhd ../../rtl/core/neorv32_slink.vhd ../../rtl/core/neorv32_spi.vhd ../../rtl/core/neorv32_sysinfo.vhd ../../rtl/core/neorv32_top.vhd ../../rtl/core/neorv32_trng.vhd ../../rtl/core/neorv32_twi.vhd ../../rtl/core/neorv32_uart.vhd ../../rtl/core/neorv32_wdt.vhd ../../rtl/core/neorv32_wishbone.vhd ../../rtl/core/neorv32_xirq.vhd devices/ice40/neorv32_imem.ice40up_spram.vhd:45:9:error: cannot find resource library "ice40" devices/ice40/neorv32_imem.ice40up_spram.vhd:46:11:error: unit "components" not found in library "ice40" devices/ice40/neorv32_imem.ice40up_spram.vhd:66:34:error: entity 'neorv32_imem' was not analysed make[3]: *** [synthesis.mk:5: neorv32-obj08.cf] Error 1
Seams that is taking iCE40 VHDL setting files instead ECP5 files (as OrangeCrab does) I couldn't find where...

…ybe optimization, ULX3S Failing for some misconfiguration in Makefiles

stnolting · 2021-08-10T16:52:50Z

Thank you very much for the contribution! 🎉

Seams that is taking iCE40 VHDL setting files instead ECP5 files (as OrangeCrab does) I couldn't find where...

No problem! We will have a look.

stnolting · 2021-08-10T17:17:49Z

Let's check the Alhambra II first.

In neorv32_AlhambraII_BoardTop_MinimalBoot.vhd you are instantiating the SB_HFOSC primitive. But does this FPGA family (iCE40HX) actually have this primitive (I am still looking through the data sheet...)?!

-> Unable to place cell 'hsosc_inst_OSC' of type 'ICESTORM_HFOSC'

Seems like the board provides an external 12MHz clock. Maybe we should use that instead. We can still use the PLL and it's default configuration.

seems like there is no HF_OSC primitive in the iCE40HX family; revert this if I am wrong ;D

stnolting · 2021-08-10T17:39:49Z

Same thing with the RGB drive. But we can just use simple IOs for that 😉

By the way, I am referring to this Alhambra II setup: https://github.com/FPGAwars/Alhambra-II-FPGA/blob/master/doc/pinout/Alhambra%20II%20V1.0A%20-%20Pinout_v1.0_rev%202.pdf
Is this the right one?

I am little bit confused about the AlhambraII.pcf. Seems like there is no RGB LED and even no PMODs or SPI ports? 🤔

zipotron · 2021-08-11T12:12:44Z

Let's check the Alhambra II first.

In neorv32_AlhambraII_BoardTop_MinimalBoot.vhd you are instantiating the SB_HFOSC primitive. But does this FPGA family (iCE40_HX_) actually have this primitive (I am still looking through the data sheet...)?!

-> Unable to place cell 'hsosc_inst_OSC' of type 'ICESTORM_HFOSC'

Seems like the board provides an external 12MHz clock. Maybe we should use that instead. We can still use the PLL and it's default configuration.

Completely agree, I did pay attention enough, this board have external clock

zipotron · 2021-08-11T12:17:54Z

Same thing with the RGB drive. But we can just use simple IOs for that wink

By the way, I am referring to this Alhambra II setup: https://github.com/FPGAwars/Alhambra-II-FPGA/blob/master/doc/pinout/Alhambra%20II%20V1.0A%20-%20Pinout_v1.0_rev%202.pdf
Is this the right one?

I am little bit confused about the AlhambraII.pcf. Seems like there is no RGB LED and even no PMODs or SPI ports? thinking

Yes, this is the right pinout document )I have it in paper!). This board have not RGB, but instead I configured in the .pcf three of the leds for just tested. PMOD there is not, but SPI yes! There is 2 SPI, one for general propose and the second one for FLASH memory!
UPS, just realized that I forgot to review the PMOD pinout... just leaved in a random pin number for don't have "unmapped constrains" during the syntheses and forgot there...

…or top of VHDL

zipotron · 2021-08-11T13:03:37Z

HI! I cleaned a bit the code regarding the PMOD and the USB. Did looks now better?
I couldn't fix the issue with the LEDS, I have this error:
Info: Packing constants.. Info: Packing IOs.. Info: AlhambraII_LED_B use by SB_RGBA_DRV/SB_RGB_DRV rgb_inst, not creating SB_IO Info: AlhambraII_LED_R use by SB_RGBA_DRV/SB_RGB_DRV rgb_inst, not creating SB_IO Info: AlhambraII_LED_G use by SB_RGBA_DRV/SB_RGB_DRV rgb_inst, not creating SB_IO Info: Packing LUT-FFs.. Info: 2664 LCs used as LUT4 only Info: 979 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 628 LCs used as DFF only Info: Packing carries.. Info: 131 LCs used as CARRY only Info: Packing RAMs.. Info: Placing PLLs.. Info: constrained PLL 'pll_inst' to X16/Y33/pll_3 Info: (given its connections, this PLL could have been a PAD PLL) Info: Packing special functions.. ERROR: Unable to place cell 'rgb_inst' of type 'SB_RGBA_DRV' ERROR: Packing design failed. 4 warnings, 2 errors
I am sure that is something deeper in the VHDL, the PWM, the Alhambra board have not hardware PWM (I always implemented the PWM in the code) and I don't know how you are using this, I would like to investigate but I have to attend a bit my job! If you guide mi I can try again later!

stnolting · 2021-08-11T15:05:49Z

HI! I cleaned a bit the code regarding the PMOD and the USB. Did looks now better?

Looks great! 👍

I couldn't fix the issue with the LEDS, I have this error:

It is the same problem as with the HF_OSC: the iCE40HX FPGAs do not provide the SB_RGBA_DRV primitive but it is instantiated in the top unit.

As the board provides 8 on-board LEDs I propose the following:

use the 4 GPIO output ports to drive LED0 .. LED3
use the 3-bit PWM output to drive LED5 .. LED7 (without the SB_RGBA_DRV primitive)

I can take care of that. Furthermore, I would remove the SPI pin mapping for now as MinimalBoot does not provide this feature anyway.

~~Another thing we should check is the mapping of the UART RX and TX ports. Do you know if pin 61 (TX) is an input or an output of the FTDI?~~ I have checked the schematics. Pin mappings look right! 😄

stnolting · 2021-08-11T15:18:06Z

Another thing I just realized is the amount of available block RAM. Is the Alhambra II board using the HX8K FPGA?

In that case we have 16kB block RAM available in total. We need 4kB for the bootloader, so we could use 8kB for the IMEM and the remaining 4kB for the DMEM.

edit

I forget the block RAM requirements of the CPU register file... 😅
So we should decrease DMEM size to 2kB.

stnolting · 2021-08-11T15:35:40Z

We have a bitstream! 🎉
-> https://github.com/stnolting/neorv32/actions/runs/1120639435

I am not sure if you can access the workflow artifact. If not, here is the bitstream (rename from *.txt to *.bit):

💾 neorv32_AlhambraII_MinimalBoot.txt

zipotron · 2021-08-11T17:53:27Z

Another thing I just realized is the amount of available block RAM. Is the Alhambra II board using the HX8K FPGA?

In that case we have 16kB block RAM available in total. We need 4kB for the bootloader, so we could use 8kB for the IMEM and the remaining 4kB for the DMEM.

edit

I forget the block RAM requirements of the CPU register file... sweat_smile
So we should decrease DMEM size to 2kB.

Yes 8K!

zipotron · 2021-08-11T17:55:15Z

We have a bitstream! tada
-> https://github.com/stnolting/neorv32/actions/runs/1120639435

I am not sure if you can access the workflow artifact. If not, here is the bitstream (rename from *.txt to *.bit):
* floppy_disk [neorv32_AlhambraII_MinimalBoot.txt](https://github.com/stnolting/neorv32/files/6969635/neorv32_AlhambraII_MinimalBoot.txt)

Synthesis OK in my side!

stnolting · 2021-08-11T18:25:03Z

Synthesis OK in my side!

Could you test the bitstream on your Alhambra board?

If everything works fine we can move on the ULX3S 👍

zipotron · 2021-08-11T19:00:55Z

Synthesis OK in my side!

Could you test the bitstream on your Alhambra board?

If everything works fine we can move on the ULX3S +1

I can not do right now, I am not in my city, I will be back on the weekend, I am not sure I will manage to test on weekend, I will try, but for sure I can do on Monday during my boring remote work meetings!

stnolting · 2021-08-11T19:06:08Z

I can not do right now, I am not in my city, I will be back on the weekend, I am not sure I will manage to test on weekend, I will try, but for sure I can do on Monday during my boring remote work meetings!

No need to rush 😉

So let's move on to the ULX3S board if you are ok with that. Btw, we are talking about this one https://radiona.org/ulx3s/, right?

There are some minor things that need to be adapted in the makefiles (like memory components) but I can take care of it. I think the only thing that is really missing is a design top entity like neorv32_ULX3S_BoardTop_MinimalBoot.vhd. Could you provide this? Again, no need to rush here. We could also do that in a follow-up pull request so we can merge the Alhambra first.

zipotron · 2021-08-11T19:06:17Z

I just push some fixes for the ULX3S board, I got stack with this error:
Info: [ 74545, 76961) |************************************************************ Info: [ 76961, 79377) |******************+ ERROR: cannot place differential IO at location PIOD 2 warnings, 1 error
Seams all constrains well set and is almost in the end of the synthesis. What is your opinion?

stnolting · 2021-08-11T19:09:23Z

Seems like my comment and your commit had a great timing 😄

Seams all constrains well set and is almost in the end of the synthesis. What is your opinion?

I will have a look tomorrow. 👍

zipotron · 2021-08-11T19:09:38Z

I can not do right now, I am not in my city, I will be back on the weekend, I am not sure I will manage to test on weekend, I will try, but for sure I can do on Monday during my boring remote work meetings!

No need to rush wink

So let's move on to the ULX3S board if you are ok with that. Btw, we are talking about this one https://radiona.org/ulx3s/, right?

There are some minor things that need to be adapted in the makefiles (like memory components) but I can take care of it. I think the only thing that is really missing is a design top entity like neorv32_ULX3S_BoardTop_MinimalBoot.vhd. Could you provide this? Again, no need to rush here. We could also do that in a follow-up pull request so we can merge the Alhambra first.

Just push that file! Yes, is this: https://radiona.org/ulx3s/ (My favourite board!).
We can merge whenever whatever and however you want, I follow you.

stnolting · 2021-08-12T11:52:14Z

I suggest the following:

Let's remove all ULX3S-related modification from this PR so that this is just "Adding AlhambraII Board". After this is merged, please fire another pull request with the ULX3S. Are you ok with this? I would take care of cleaning up this PR.

Alternatively, we can keep on working on the ULX3S here and merge everything when that setup is also running.

zipotron · 2021-08-12T12:50:05Z

Well, as long as I can not test the boards until next week I would suggest to keep working in this PR, and next week when I test the two board merge everything. But is just an opinion, we do as you prefer, is your repo and I respect that, and thanks for ask my opinion, really appreciate!

zipotron · 2021-08-17T07:03:20Z

Hi!, The AlhambraII have two USB ports, but one is just for power, no data, If I remember good, with PicoRV32 I could connect throw serial, using the same USB port, and when flash the bit stream and boot the board, appears a second USB serial block device in the /dev directory. Anyway, I would start with a version that make blink one LED, and then go step forward to the UART connection.
I am going a try ASAP this new bit stream, also I updated my Fedora and I want to compile again all the tools. Just, I have quite difficult days at work and maybe I will take a bit more time to do it.

stnolting · 2021-08-17T13:45:29Z

Anyway, I would start with a version that make blink one LED

Good idea. The current Alhambra setup uses the bootloader, which shows a "heart beat" using the LED at GPIO output pin 0. If we still have problems making the first bitstream run, we could further simplify the setup by using the much simpler "minimal "SoC configuration: that SoC does not use the bootloader and boots a pre-installed LED blink program instead.

I am going a try ASAP this new bit stream, also I updated my Fedora and I want to compile again all the tools.

Fingers crossed! 😉

Just, I have quite difficult days at work and maybe I will take a bit more time to do it.

No worries! Take your time.

zipotron · 2021-08-18T17:10:58Z

Please try the updated bitstream from: https://github.com/stnolting/neorv32/actions/runs/1135206641

AlhambraII seams working! The first led is blinking 16 times, like two pulses per second, and after that staying on, and appears another USB serial file "/dev/ttyUSB1", but UART stills refusing connection, I tried with 115200 and 9600. Anyway seams working!
I am going a try the ULX3S...

zipotron · 2021-08-18T17:23:47Z

With ULX3S I had not the same results, no blinking any led, and didn't appears a extra USB serial file in my Linux.
Now I am going a try to fix my environment, I couldn't find time to do it until now, as soon as I have a working synthesis I will try to investigate what is going bad with ULX3S.

stnolting · 2021-08-19T12:21:44Z

AlhambraII seams working!

Awesome! 🎉

The first led is blinking 16 times, like two pulses per second, and after that staying on, and appears another USB serial file "/dev/ttyUSB1", but UART stills refusing connection, I tried with 115200 and 9600. Anyway seams working!
I am going a try the ULX3S...

That is the heart beat blinking of the bootloader. The default Baud rate is 19200. If nothing appears in the terminal try a reset of the FPGA. Maybe we have switched the TX and RX signals... 🤔

Btw, did you use the bitstream from the project's workflow or did you generate it locally on your machine?

With ULX3S I had not the same results, no blinking any led, and didn't appears a extra USB serial file in my Linux.

I will have a look again.

zipotron · 2021-08-19T13:21:47Z

AlhambraII seams working!

Awesome! tada

The first led is blinking 16 times, like two pulses per second, and after that staying on, and appears another USB serial file "/dev/ttyUSB1", but UART stills refusing connection, I tried with 115200 and 9600. Anyway seams working!
I am going a try the ULX3S...

That is the heart beat blinking of the bootloader. The default Baud rate is 19200. If nothing appears in the terminal try a reset of the FPGA. Maybe we have switched the TX and RX signals... thinking

Btw, did you use the bitstream from the project's workflow or did you generate it locally on your machine?

With ULX3S I had not the same results, no blinking any led, and didn't appears a extra USB serial file in my Linux.

I will have a look again.

Hi!
I tried AlhambraII with the 19200 baud rate, the "/dev/ttyUSB0" and "/dev/ttyUSB1", and pressing reset, no connection, I would like to try switching TX and RX, but, I couldn't finish to fix my environment, not too much free time this week...
Bitstream from the project's workflow, I recompiled yesterday Yosys GHDL NextPNR... But couldn't test yet...

zipotron · 2021-08-19T13:33:19Z

AlhambraII seams working!

Awesome! tada

The first led is blinking 16 times, like two pulses per second, and after that staying on, and appears another USB serial file "/dev/ttyUSB1", but UART stills refusing connection, I tried with 115200 and 9600. Anyway seams working!
I am going a try the ULX3S...

That is the heart beat blinking of the bootloader. The default Baud rate is 19200. If nothing appears in the terminal try a reset of the FPGA. Maybe we have switched the TX and RX signals... thinking
Btw, did you use the bitstream from the project's workflow or did you generate it locally on your machine?

With ULX3S I had not the same results, no blinking any led, and didn't appears a extra USB serial file in my Linux.

I will have a look again.

Hi!
I tried AlhambraII with the 19200 baud rate, the "/dev/ttyUSB0" and "/dev/ttyUSB1", and pressing reset, no connection, I would like to try switching TX and RX, but, I couldn't finish to fix my environment, not too much free time this week...
Bitstream from the project's workflow, I recompiled yesterday Yosys GHDL NextPNR... But couldn't test yet...

I just test my environment, I can synthesize again, I can play again! I will try to switch TX and RX in AlhambraII and test the UART, tonight or tomorrow night, as soon as I get a bit of free time

stnolting · 2021-08-19T15:13:13Z

I tried AlhambraII with the 19200 baud rate, the "/dev/ttyUSB0" and "/dev/ttyUSB1", and pressing reset, no connection, I would like to try switching TX and RX, but, I couldn't finish to fix my environment, not too much free time this week...

Please double check your computer's tty configuration. Seems like there are RX and TX LEDs on the Alhambra board. If you connect to the UART USB port, you should see the TX LED flashing when you type something into the terminal program - regardless of the FPGA content.

zipotron · 2021-08-19T19:59:19Z

Hi! Definitely you were right, I check the constrains file and the alhambraII datasheet and TX, RX was flipped (My fault, sorry). But, from last merge "master" to this branch is not appearing any more the UART block device, not with flipped constrains or fixed ones.

stnolting · 2021-08-20T08:03:53Z

Hi! Definitely you were right, I check the constrains file and the alhambraII datasheet and TX, RX was flipped (My fault, sorry).

👍

But, from last merge "master" to this branch is not appearing any more the UART block device, not with flipped constrains or fixed ones.

What do you mean? The UART is still listed in the synthesis flow so there should be no difference in the hardware. The available tty devices in your Linux device tree should not be impacted by this at all. It is the on-board FTDI chip that provides these USB devices and not the FPGA or it's programmed logic.

zipotron · 2021-08-22T11:11:05Z

Hi! Definitely you were right, I check the constrains file and the alhambraII datasheet and TX, RX was flipped (My fault, sorry).

+1

But, from last merge "master" to this branch is not appearing any more the UART block device, not with flipped constrains or fixed ones.

What do you mean? The UART is still listed in the synthesis flow so there should be no difference in the hardware. The available tty devices in your Linux device tree should not be impacted by this at all. It is the on-board FTDI chip that provides these USB devices and not the FPGA or it's programmed logic.

I mean that before that merge was appearing a extra "tty" in the linux device tree (the programmer and another one), as happens also when you flash the Picorv32 SOC for AlhambraII, and after the merge (without changing anything) do not appears anymore...
I don't know why because I didn't go throw the changes, last days I really had very little free time. First days of next week are going a be hard, but maybe latter, closer to the weekend I can be a bit more on this (even if I can, don't expect too much, you have a lot of code and I am not very familiar with this project yet).
Another question, how can I help you for make the ULX3S works?

zipotron · 2021-08-28T13:44:35Z

@stnolting I could manage to connect throw the serial to the AlhambraII board, the issue was in my environment, I forgot to give the right permission to the ttyUSB1 block device, now I can connect to the board and Putty report "connected successfully" but no anything more, if I do "echo -ne '\033[2J' > /dev/ttyUSB1" I can see the UART led blinking in the board. I will give a bit time to ULX3S, maybe working around I can take the same result...

stnolting · 2021-08-29T12:39:59Z

Hey there!
Sorry for the late answer - I was quite busy this week 😉

Good to hear the UART connection is working!
You could try to make a local UART echo in the FPGA to check if the physical pin mapping (and the actual configuration / bitstream generation) is working as expected. In neorv32_AlhambraII_BoardTop_MinimalBoot.vhd change the processor's UART connection

    uart_txd_o => open, -- UART0 send data (NOT USED)
    uart_rxd_i => AlhambraII_RX, -- UART0 receive data

and add this line somewhere

AlhambraII_TX <= AlhambraII_RX;

zipotron · 2021-08-29T19:26:44Z

Hi, no worries! I use to be busy too!
I tried the echo, and couldn't get answer, the UART led blink when you print characters
(stty ospeed 19200 < /dev/ttyUSB1; exec 99<>/dev/ttyUSB1; printf "AT\r" >&99) But Putty don't print back nothing,
I did the suggested modifications:
` port map (
-- Global control --
clk_i => std_ulogic(AlhambraII_CLK),
rstn_i => std_ulogic(sys_rstn),

-- GPIO --
gpio_o     => con_gpio_o,

-- primary UART --
uart_txd_o => open, -- UART0 send data (NOT USED)
uart_rxd_i => AlhambraII_RX, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0',  -- hw flow control: UART0.TX allowed to transmit, low-active, optional

-- PWM (to on-board RGB LED) --
pwm_o      => con_pwm`

);

-- IO Connection -------------------------------------------------------------------------- -- -------------------------------------------------------------------------------------------
AlhambraII_LED0 <= con_gpio_o(0); AlhambraII_LED1 <= con_gpio_o(1); AlhambraII_LED2 <= con_gpio_o(2); AlhambraII_LED3 <= con_gpio_o(3); AlhambraII_LED4 <= '0'; -- unused AlhambraII_LED5 <= con_pwm(0); AlhambraII_LED6 <= con_pwm(1); AlhambraII_LED7 <= con_pwm(2); AlhambraII_TX <= AlhambraII_RX;
I will play around a bit... in the main time if you have any suggestion...
UPDATE
I tried this:
AlhambraII_LED0 <= con_gpio_o(0); AlhambraII_LED1 <= AlhambraII_RX; AlhambraII_LED2 <= AlhambraII_TX; AlhambraII_LED3 <= con_gpio_o(3); AlhambraII_LED4 <= '0'; -- unused AlhambraII_LED5 <= con_pwm(0); AlhambraII_LED6 <= con_pwm(1); AlhambraII_LED7 <= con_pwm(2);
It suppose to make blink the 2th and the 3th LED in UART transfer. They are not blinking..., are on just

stnolting · 2021-08-29T20:02:47Z

I have checked the Alhambra schematics again. As far as I understand, the FTDI UART interface looks like this:

FTDI chip TX output (BDBUS0) -> schematic net FT_TX -> FPGA pin 62 (IOB_102) -> VHDL input AlhambraII_RX
FTDI chip RX input (BDBUS1) <- schematic net FT_RX <- FPGA pin 61 (IOB_96) <- VHDL output AlhambraII_TX

If this is correct, then the current setups/osflow/constraints/AlhambraII.pcf constraints file is wrong because RX and TX are flipped. I think it should be like this:

# UART port (on-board FTDI)
set_io AlhambraII_TX 61  # FPGA output, FTDI input
set_io AlhambraII_RX 62  # FPGA input, FTDI output

…rx reacting

zipotron · 2021-08-29T20:37:59Z

Good news, at last, I managed to make the ULX3S works, I push some changes, hart led is blinking, (I reconnect temporally the 2th and the 3th led to the TX and RX just for see if works, I will delete this dirty code in the next push) UART is working!!

stnolting · 2021-08-29T20:40:03Z

Good news, at last, I managed to make the ULX3S works, I push some changes, hart led is blinking, (I reconnect temporally the 2th and the 3th led to the TX and RX just for see if works, I will delete this dirty code in the next push) UART is working!!

Awesome news!! 👍 🎉

zipotron · 2021-08-29T20:45:24Z

And more good news! You were right, I check again everything flipping the RX and TX in AlhambraII and was that, I don't know why I got confused with the datasheet, I checked... Maybe I am dyslexic? Now the two boards are working!
What is the next steep?
Update
I am not dyslexic:

stnolting · 2021-08-29T20:55:48Z

And more good news! You were right, I check again everything flipping the RX and TX in AlhambraII and was that, I don't know why I got confused with the datasheet, I checked... Maybe I am dyslexic? Now the two boards are working!
What is the next steep?

Hooray! 🎉
I am so happy to hear the setups are working 😄 Thank you very much for your great work and effort!

It would be great if you could test the bitstreams generated by the Implementation workflow here. If these bitstreams are working, then we can merge everything 👍

edit

I don't know why I got confused with the datasheet, I checked... Maybe I am dyslexic? Now the two boards are working!
What is the next steep?
Update
I am not dyslexic:

Do not worry about that at all! The UART's RX and TX signal declarations are never really clear in most pin diagrams. You have a 50:50 chance of selecting the right wiring - and in my case I always take the wrong one first 😄

zipotron · 2021-08-30T16:40:20Z

I just tested the bitstreams generated by the Implementation workflow, and are working! I think is ready for merge.
It was a pleasure to collaborate in this project, and I hope to contribute soon and often!

stnolting · 2021-08-30T19:14:13Z

I just tested the bitstreams generated by the Implementation workflow, and are working! I think is ready for merge.

Great! I will have a final look at all the changed files and will merge everything after that. 🚀

It was a pleasure to collaborate in this project, and I hope to contribute soon and often!

Thank you very much! It was also a pleasure for me.
Let's see what cool features we will come up with in the future 😉

umarcor · 2021-09-13T03:49:49Z

For the record, on Windows I recommend using MSYS2. Just install it, update, and then:

pacman -S mingw-w64-x86_64-eda

That provides several open source EDA tools, including GHDL, Yosys, nextpnr, etc.: https://packages.msys2.org/group/mingw-w64-x86_64-eda
See https://hdl.github.io/MINGW-packages/.

Alternatively, containers from https://hdl.github.io/containers/ can be used with Docker Desktop.

Both approaches are used/showcased in the CI of this repo.

Added AlhambraII and ULX3S boards, Alhambra failing in the design, ma…

f1f25c5

…ybe optimization, ULX3S Failing for some misconfiguration in Makefiles

[.github] added AlhambraII board (PR) to Implementation workflow

0bd9865

removed HF_OSC; using external clock [TEST]

39dc746

seems like there is no HF_OSC primitive in the iCE40HX family; revert this if I am wrong ;D

PMOD references removed from .pcf file. Unexistent USB port removed f…

2e5c884

…or top of VHDL

stnolting added 2 commits August 11, 2021 17:06

removed SPI pins; added all on-board LED pins

071b63d

removed RGB drive; added on-board LEDs

e777498

stnolting added 3 commits August 11, 2021 17:18

8kB IMEM; 4kB DMEM

8903de5

DMEM = 2kB

20b219c

fixed memory HDL include

bff5293

stnolting mentioned this pull request Aug 11, 2021

Move osflow examples #137

Merged

ULX3S Synthesis fix

87525f3

stnolting and others added 2 commits August 19, 2021 17:43

Merge branch 'master' into pr/139

2b8daf6

Bugfix - UART TX and RX constrains was fliped

67ef58f

ULX3S Working, hart led blinking, UART connection suscess and tx and …

195adb7

…rx reacting

AlhambraII working, UART issue fixed, ULX3S dirty code cleaned

58d20c5

ULX3S rewired reset button, and code cleaned

bb3b936

stnolting approved these changes Aug 31, 2021

View reviewed changes

stnolting merged commit 79058c1 into stnolting:master Aug 31, 2021

zipotron deleted the AlhambraII_and_ULX3S_boards branch September 1, 2021 08:31

Added AlhambraII and ULX3S boards #139

Added AlhambraII and ULX3S boards #139

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