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Ruige Lee edited this page Jan 20, 2021 · 4 revisions

RiftCore

Welcome to the RiftCore wiki!

RiftCore is a 9-stage, multi-issue, out of order 64-bits RISC-V Core, which partially supports RV64IMC.

Pineline

  • PC Generate

  • instruction fetch

  • instruction queue

  • instruction decode

  • dispatch (and rename)

  • issue ( and read op)

  • execute

  • writeback

  • commit (and reOrder)

architecture

Home

pc generate

instruction fetch

instruction queue

instruction decode

instruction FIFO

dispatch

issue

execute

writeback

commit

out of order implementation

Parity memory

inner bus

FPGA Implementation

Basic Element

D Flip-Flop

D Flip-Flop with enable

RS Flip-Flop

Sync FIFO

Bypass FIFO

Ring Stack

SRAM

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