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Ruige Lee edited this page Dec 31, 2020 · 2 revisions

execute

In this version, there are 5 execution units implemented.

  • alu
  • bru
  • csr
  • lsu
  • mul

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pc generate

instruction fetch

instruction queue

instruction decode

instruction FIFO

dispatch

issue

execute

writeback

commit

out of order implementation

Parity memory

inner bus

FPGA Implementation

Basic Element

D Flip-Flop

D Flip-Flop with enable

RS Flip-Flop

Sync FIFO

Bypass FIFO

Ring Stack

SRAM

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