Parity memory
Both hardware and software solution is allowed to implement an address unaligned LSU.
- In a software implementation, an exception will occur when unaligned access happens. Two align access will be produced in exception. It's not an effective solution that the pipeline will flush and two memory access is required.
- In a hardware implementation, a parity memory is required to implement in a level of memory. In this version, a parity CCM is implemented. The following version is to implement a cache with parity memory.
The hardware of the memory is implemented as one address corresponding to one data. When the access address is not aligned, no matter how wide the memory hardware is used, there is a possibility that the memory access address may fall between the two hardware addresses. At this time, complete data cannot be obtained in one fetch. Therefore, when designing a memory with unaligned access, it is necessary to design more than two BANKs. After the data is split, it is stored in multiple memory entities and combined for access. The combined data bit width needs to be twice the maximum bit width of the memory fetch to ensure full coverage for one access.
