v1.6.8

What's Changed

• ✨[Zxcfu ISA ext.] add option to implement custom RISC-V instructions by @stnolting in #264
• 🐛 [sw] fixed bug in bootloader's (M)TIME handling by @stnolting in #267
• 🧪 Using LTO (link-time-optimization) for bootloader + console improvements by @stnolting in #268
• [docs/datasheet] rework & update NEORV32 runtime environment (RTE) section by @stnolting in #272
• [rtl] add err_o signal to IMEM modules by @stnolting in #273
• ✨ [rtl] on-chip debugger: add RISC-V trigger module for hardware breakpoints by @stnolting in #274
• [sw] add support for newlib's system calls by @stnolting in #275
• ⚠️ replace SYSINFO.CPU memory-mapped register by custom "mxisa" CSR by @stnolting in #276
• [OCD] stop CPU counters during debugging by @stnolting in #277
• Add newlib example program and documentation by @stnolting in #278

Full Changelog: v1.6.7...v1.6.8