✨ [rtl] on-chip debugger: add RISC-V trigger module for hardware breakpoints #274
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🐛 minor bug fix in "ebreak" instruction's dcsr.cause value (was "2", but has to be "1")
stnolting
added
risc-v compliance
added "hardware" breakpoint example
reworked whole section "on-chip debugger"
add RISC-V trigger module to CPU / debugger
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This PR adds a simple implementation of the RISC-V trigger module to the CPU core. It complies to the RISC-V debug spec. v0.13.2. A copy of this spec. can be found in docs/references.
💡 The NEORV32 trigger module is part of the on-chip debugger and implements a single instruction address match trigger that can be used to add "hardware-assisted breakpoints" when debugging code that is executed from ROM.
The idea to add this was triggered by @emb4fun.
Hardware Breakpoints vs. Software Breakpoints
The "normal" software breakpoints using gdb's
b/breakcommand temporarily replace the instruction word, where the debugger shall halt, by a BREAK instruction (ebreakorc.ebreak). After the CPU has halted and entered debug mode, the debugger will restore the original instruction word to maintain correct operation. Obviously, this concept is only possible when the program being executed resides in RAM.Example: Adding a software breakpoint at address 0xffff0000 in gdb:
b *0xffff0000When debugging code, which is executed from ROM, one needs to use hardware-assisted breakpoints using gdb's
hb/hbreakcommands. A hardware breakpoint uses the CPU's trigger module to store the address of the instruction that shall trigger a breakpoint. Whenever execution reaches this specific address the CPU is halted and enters debug mode.Example: Adding a hardware-assisted breakpoint at address 0xffff0000 in gdb:
hb *0xffff0000🐛 This PR also fixes a minor bug in
ebreakinstruction'sdcsr.causevalue (was 0b010 but has to be 0b001).