[OCD] stop CPU counters during debugging #277
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standard CPU counters (cycle & instret CSRs) and all HPM counters are **stopped** when the CPU is in debug mode
stop counters only when the CPU is actually _in_ debug mode
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As illustrated in riscv/riscv-debug-spec#638 this PR hardwires the
dcsr.stopcountbit to1. Thus, all standard CPU counters ([m]cycle[h]and[m]instret[h]) and all hardware performance monitor (HPM) counters are always stopped during debugging (when the CPU is in debug mode).Note that the
[m]time[h]CSRs are not affected by this since they are a shadow copy of the MTIME system timer, which keeps running also during debugging (hence,dcsr.stoptimeis hardwired to0).