Skip to content

Issues: openhwgroup/cva6

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

175 Open 799 Closed
175 Open 799 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

[BUG] How to verify the output of an addi instruction? notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2321 opened Jul 4, 2024 by ais77
1 task done
1
Unable to synthesize using Yosys notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2319 opened Jul 4, 2024 by Harshitha276
1 task done
3
[TASK] Upgrade Spike tandem with DPI functions to access CSRs and to update with Interrupt/Debug signals
#2317 opened Jul 3, 2024 by AnouarZajni
1 task done
Genesys 2 UART port disables on connect
#2308 opened Jul 2, 2024 by benlarsendk
[BUG] Linking error: undefined reference to htif_t::load_payload Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2298 opened Jun 27, 2024 by shreyas-kalikar
1 task done
3
[BUG] minstret and mcycle do not increment in debug mode, while dcsr.stopcount is set to 0 (normal mode) notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2297 opened Jun 27, 2024 by xiaoweish
1 task done
5
Error while running riscv-arch-test
#2290 opened Jun 24, 2024 by abhikutari
1
[BUG] stall_instr_fetch signal in core/id_stage.sv will not be driven if CVA6Cfg.RVZCMP is disabled notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2289 opened Jun 23, 2024 by ckf104
1 task done
[BUG] B extension: incorrect decoding for some instructions in RV32 Component:RTL For issues in the RTL (e.g. for files in the rtl directory) CV32A65X Part: Embedded configuration Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2280 opened Jun 20, 2024 by ASintzoff
1 task done
@JeanRochCoulon
2
[TASK] Implement CVXIF 1.0.0 instruction dedicated to verification Component:SpikeTandem Issue that impacts Spike Tandem operation Component:Verif For issues in the verification environment or test cases (e.g. for testbench, C code, etc.) Type:Task Project related task
#2277 opened Jun 20, 2024 by Gchauvon
1 task done
Fix the 65x CSR document Component:Doc For issues in the Documentation (e.g. for README.md files) PARAM:CSR CSR Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2275 opened Jun 20, 2024 by JeanRochCoulon
@zchamski
2
[BUG] "Virtual" test list fails when icache settings are modified Component:RTL For issues in the RTL (e.g. for files in the rtl directory) notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2252 opened Jun 13, 2024 by LQUA
1 task done
[BUG] Cannot run verif/regress/benchmark.sh Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2250 opened Jun 13, 2024 by ferrandf
1 task done
1
1
latch detection in spyglass audit report Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2247 opened Jun 12, 2024 by Asmaa-Kassimi
1 task done
@JeanRochCoulon @ASintzoff
1
[BUG] SPIKE model is not configurable with TvalEn core option Component:SpikeTandem Issue that impacts Spike Tandem operation Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2243 opened Jun 12, 2024 by LQUA
1 task done
@zchamski
1
GCC 13.1.0 Prerequisites to run benchmark.sh Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2230 opened Jun 11, 2024 by Tanishqgithub
1 task done
4
Reduce gate count of csr_regfile.sv Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Enhancement For feature requests and enhancements
#2219 opened Jun 10, 2024 by JeanRochCoulon
TIME/TIMEH not implemented Component:RTL For issues in the RTL (e.g. for files in the rtl directory) notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2218 opened Jun 10, 2024 by JeanRochCoulon
Fix Camel style for cva6 parameters Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2217 opened Jun 10, 2024 by JeanRochCoulon
1
[TASK] [FPGA] Support for Xilinx AXI 1G/2.5 G Ethernet Subsystem notCV32A65X It is not an CV32A65X issue
#2213 opened Jun 7, 2024 by WorldofJARcraft
1 task done
@jquevremont
6
[BUG] Cacheable regions PMA attribute not compatible with AXI memory type signal Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2143 opened May 22, 2024 by abdelhak-chkirid
1 task done
[BUG] Cadence Xcelium dependent checksum verilog_package doesn't match notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2136 opened May 21, 2024 by yunuseryilmaz18
1 task done
3
[BUG] Incorrectly set fflags: An underflow exception is triggered when the computed result is an exact subnormal number. notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2129 opened May 18, 2024 by fly-1011
1 task done
4
[BUG] Linux boot on Nexys Video CVA6 64-bit configuration notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2116 opened May 15, 2024 by amiroshni
1 task done
3
Create riscv-config dependency between RVD and XLEN notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
#2113 opened May 15, 2024 by JeanRochCoulon
1 task done
ProTip! no:milestone will show everything without a milestone.