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[BUG] Cacheable regions PMA attribute not compatible with AXI memory type signal #2143

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abdelhak-chkirid opened this issue May 22, 2024 · 0 comments
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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@abdelhak-chkirid
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Is there an existing CVA6 bug for this?

  • I have searched the existing bug issues

Bug Description

Illegal memory access to the cacheable region (8000_0000 <= address <= c000_0000) due to a mismatch between the AXI bus and the PMA rules.
The ARCACHE signal in the AXI interface indicates that the memory type is NonCacheable, but the PMA is configured as cacheable in this memory region.

@abdelhak-chkirid abdelhak-chkirid added the Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system label May 22, 2024
@JeanRochCoulon JeanRochCoulon added the Component:RTL For issues in the RTL (e.g. for files in the rtl directory) label Jun 20, 2024
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Labels
Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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