[BUG] Cacheable regions PMA attribute not compatible with AXI memory type signal #2143
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Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
Is there an existing CVA6 bug for this?
Bug Description
Illegal memory access to the cacheable region (8000_0000 <= address <= c000_0000) due to a mismatch between the AXI bus and the PMA rules.
The ARCACHE signal in the AXI interface indicates that the memory type is NonCacheable, but the PMA is configured as cacheable in this memory region.
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