[BUG] minstret
and mcycle
do not increment in debug mode, while dcsr.stopcount
is set to 0 (normal mode)
#2297
Labels
notCV32A65X
It is not an CV32A65X issue
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
Is there an existing CVA6 bug for this?
Bug Description
When
debug_req_i
is asserted and DUT enters into debug mode,minstret
andmcycle
do not increment in debug mode (whiledcsr.stopcount==0
), as below figure shows,riscv-debug-spec says,
also, here
So, we can see that current cva6 behavior:
minstret
andmcycle
stopped is conflict with itsdcsr.stopcount==0
setting.The text was updated successfully, but these errors were encountered: