dig_it_all

Workspace to learn basic digital design techniques and languages.

Current content

• Simple VHDL example, which I'm using to refresh my familiarity with digital design and to learn GHDL.
• Same example, implemented in Verilog, used mostly to learn the language and to learn about 2 tools: Icarus Verilog and Verilator

Getting started

A first VHDL test-bench for a simple sequence cycler can be run following the basics steps noted down here.
An equivalent example in Verilog can be run following the steps noted here.

TODO:

• create a proper script for GHDL (e.g. based on GHDL command notes).
• implement blind_cycler in Verilog (sim with Icarus Verilog)
• implement blind_cycler in SystemVerilog (sim with Verilator) no need, same as Verilog
• separate source files according to language