{"payload":{"header_redesign_enabled":false,"results":[{"id":"581119748","archived":false,"color":"#adb2cb","followers":0,"has_funding_file":false,"hl_name":"mzannoni/dig_it_all","hl_trunc_description":"Digital IC design playground","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":581119748,"name":"dig_it_all","owner_id":29273478,"owner_login":"mzannoni","updated_at":"2024-05-13T11:24:36.795Z","has_issues":true}},"sponsorable":false,"topics":["digital","vhdl","verilog","systemverilog","ic"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":69,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Amzannoni%252Fdig_it_all%2B%2Blanguage%253AVHDL","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/mzannoni/dig_it_all/star":{"post":"AE56c03CJ8ytsvuwSOClIMts8g2xPKWPY2U474OQq2YOkO1ZEk8Haq4ZAa21Y2vOTvgzfatGMMxR9bi4VRSROg"},"/mzannoni/dig_it_all/unstar":{"post":"bSQrJUklNdpxULEox636YciR-Uhd3-oWizILCU2rFCnmmg_g2LeIgPGMJdeEt1axabPU-7OM_h26q_QVjX8-Ng"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"iG6QKP8LxH1-XeUi6-_aMnvur5d26W3ZqU2QZ69sQ-d0ZTO1JmZ2Q1hswTbuDjawNu76OB0qUgDHPw94ivy7Vg"}}},"title":"Repository search results"}