Westmere

Architecture specific notes for Intel® Westmere

The Intel® Westmere microarchitecture has the same features as the Intel® Nehalem architecture. There are some additional features like a second OFFCORE_RESPONSE register and an addr/opcode matching unit for general-purpose counters in the Uncore.

Performance groups

Intel® Westmere Performance groups

Events

The input file for the events on Intel® Westmere can be found here.

Counters

Fixed-purpose counters

Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose counters. Each can measure only one specific event. They are core-local, hence each hardware thread has its own set of fixed counters.

Counters

Counter name	Event name
FIXC0	INSTR_RETIRED_ANY
FIXC1	CPU_CLK_UNHALTED_CORE
FIXC2	CPU_CLK_UNHALTED_REF

#### Available Options

Option	Argument	Description	Comment
anythread	N	Set bit 2+(index*4) in config register
kernel	N	Set bit (index*4) in config register

### General-purpose counters The Intel® Westmere microarchitecture provides 4 general-purpose counters consisting of a config and a counter register. They are core-local, hence each hardware thread has its own set of general-purpose counters. #### Counters

Counter name	Event name
PMC0	*
PMC1	*
PMC2	*
PMC3	*

#### Available Options

Option	Argument	Description	Comment
edgedetect	N	Set bit 18 in config register
kernel	N	Set bit 17 in config register
anythread	N	Set bit 21 in config register
threshold	8 bit hex value	Set bits 24-31 in config register
invert	N	Set bit 23 in config register

#### Special handling for events The Intel® Westmere microarchitecture provides measuring of offcore events in PMC counters. Therefore the stream of offcore events must be filtered using the OFFCORE_RESPONSE registers. The Intel® Westmere microarchitecture has two of those registers. Own filtering can be applied with the OFFCORE_RESPONSE_0_OPTIONS and OFFCORE_RESPONSE_1_OPTIONS events. Only for those events two more counter options are available:

Option	Argument	Description	Comment
match0	8 bit hex value	Input value masked with 0xFF and written to bits 0-7 in the OFFCORE_RESPONSE register	Check the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring and the event files at https://download.01.org/perfmon/WSM-EP-SP.
match1	8 bit hex value	Input value masked with 0xF7 and written to bits 8-15 in the OFFCORE_RESPONSE register	Check the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring and the event files at https://download.01.org/perfmon/WSM-EP-SP.

Fixed-purpose Uncore counters

The Intel® Westmere microarchitecture provides offers fixed-purpose counter to measure the clock frequency of the Uncore.

Counters

Counter name	Event name
UPMCFIX	UNCORE_CLOCKTICKS

General-purpose Uncore counters

The Intel® Westmere microarchitecture provides 8 general-purpose counters consisting of a config and a counter register.

Counters

Counter name	Event name
UPMC0	*
UPMC1	*
UPMC2	*
UPMC3	*
UPMC4	*
UPMC5	*
UPMC6	*
UPMC7	*

#### Available Options

Option	Argument	Description	Comment
edgedetect	N	Set bit 18 in config register
anythread	N	Set bit 21 in config register
threshold	8 bit hex value	Set bits 24-31 in config register
invert	N	Set bit 23 in config register
opcode	8 bit hex value	Set bits 40-47 in MSR_UNCORE_ADDR_OPCODE_MATCH register	A list of valid opcodes can be found in the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring.
match0	40 bit physical memory address	Extract bits 3-39 from address and write them to bits 3-39 in MSR_UNCORE_ADDR_OPCODE_MATCH register