Marvell Thunder X2

Architecture specific notes for Marvell® Thunder X2 (ARMv8)

Currently no options are available for Marvell® Thunder X2 (ARMv8). All handling is managed by perf_event.

Performance groups

Marvell® Thunder X2 Performance groups

Events

The input file for the events on Marvell® Thunder X2 (ARMv8) can be found here.

Counters

• Core-local counters
  • General-purpose counters
• Socket-local counters
  • Last-level-cache counters
  • DDR4 Memory Controller (DMC) counters
  • Marvell Coherent Processor Interconnect (CCPI) counters

Core-local counters

General-purpose counters

The Marvell® Thunder X2 (ARMv8) microarchitecture provides 6 general-purpose counters, similar to default ARM® A57, consisting of a config and a counter register.

Counter name	Event name
PMC0	*
PMC1	*
PMC2	*
PMC3	*
PMC4	*
PMC5	*

Socket-local counters

Last-level-cache counters

The Marvell® Thunder X2 (ARMv8) microarchitecture has a last level cache compared to reference implementations of ARMv8.

Counter name	Event name
CBOX<0,1>C0	*
CBOX<0,1>C1	*
CBOX<0,1>C2	*
CBOX<0,1>C3	*

DDR4 Memory Controller (DMC)

In the Marvell® Thunder X2 (ARMv8) microarchitecture each CPU socket is equipped with two memory controllers. Each controller provides 4 counters.

Counter name	Event name
MBOX<0,1>C0	*
MBOX<0,1>C1	*
MBOX<0,1>C2	*
MBOX<0,1>C3	*

Marvell Coherent Processor Interconnect (CCPI) counters

The Marvell® Thunder X2 (ARMv8) microarchitecture connects CPU sockets with the CCPI interconnect. There are two endpoints per CPU socket, each providing 8 counters.

Counter name	Event name
SBOX<0,1>C0	*
SBOX<0,1>C1	*
SBOX<0,1>C2	*
SBOX<0,1>C3	*
SBOX<0,1>C4	*
SBOX<0,1>C5	*
SBOX<0,1>C6	*
SBOX<0,1>C7	*