v1.8.1

What's Changed

• [docs] add note about platform specific DTMs by @NikLeberg in #482
• 💄 [docs] update/rework figures by @stnolting in #483
• [rtl] Cleanup CPU interrupt controller by @stnolting in #484
• [rtl] rework mip csr by @stnolting in #486
• [rtl] CPU control optimization by @stnolting in #487
• [rtl] CPU: use record as main control bus type by @stnolting in #489
• [rtl] add co-processor timing monitor by @stnolting in #490
• [sw/lib/include/neorv32.h]: remove redundant uart typedef by @akaeba in #493
• ⚠️ Replace IO_GPIO_EN generic by @stnolting in #491
• [rtl] minor trap logic optimizations and fixes by @stnolting in #497
• Add run.py dump of VHDL-LS library mapping by @kraigher in #494
• [sw] add '_zicsr' to default MARCH configuration by @stnolting in #496
• 🐛 [rtl] fix bug in co-processor monitor by @stnolting in #500
• ⚠️ constrain & relocate PWM module by @stnolting in #501
• ⚠️ remove SLINK module by @stnolting in #502

New Contributors

• @NikLeberg made their first contribution in #482
• @kraigher made their first contribution in #494

Full Changelog: v1.8.0...v1.8.1