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[rtl] rework mip csr #486

Merged
merged 7 commits into from
Feb 4, 2023
Merged

[rtl] rework mip csr #486

merged 7 commits into from
Feb 4, 2023

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stnolting
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  • cleanup CPU's trap controller VHDL code
  • fix mip CSR: bits in this register can now become set when the according interrupt source fire without the according mie CSR bit being set (RISC-V compatibility)

@stnolting stnolting added risc-v compliance Modification to comply with official RISC-V specs. HW hardware-related labels Feb 4, 2023
@stnolting stnolting self-assigned this Feb 4, 2023
@stnolting stnolting marked this pull request as ready for review February 4, 2023 16:48
@stnolting stnolting merged commit b9c2e5f into main Feb 4, 2023
@stnolting stnolting deleted the mip_rework branch February 4, 2023 17:00
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HW hardware-related risc-v compliance Modification to comply with official RISC-V specs.
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