v1.7.5

What's Changed

• 🐛 [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates by @stnolting in #367
• 🐛 [rtl] fix PMP config by @stnolting in #368
• [rtl] minor edits and updates by @stnolting in #369
• [ug] add new section "LiteX Support" by @stnolting in #370
• 🔒 Specifiy Physical Memory Attributes by @stnolting in #372
• [rtl] add CUSTOM_ID generic by @stnolting in #374
• [sw] add ISR based SPI data flow example by @akaeba in #373
• ⚠️ [linker script] simplify memory configuration by @stnolting in #375
• ⚠️ [rtl] rework SLINK module by @stnolting in #377
• [sw example] demo_spi_irq can handle FIFO by @akaeba in #382
• ✨ [rtl] add optional SPI data FIFO by @stnolting in #381
• [rtl] minor cleanups and optimizations by @stnolting in #383
• [rtl] minor cleanup by @stnolting in #384

Full Changelog: v1.7.4...v1.7.5