⚠️ [rtl] rework SLINK module

[stnolting]

This PR is another rework of the the processor's Stream Link (SLINK) module, triggered by @betocool-prog (#376).

⚠️ The module's register addresses and register contents are modified and are not backwards compatible!

• add dedicated RX_STATUS and TX_STATUS registers that expose all FIFO's status signals (empty, at least half full, full) and "last element" signals
• add IRQ register to configure interrupt conditions per-link
• RX interrupt options:
  • FIFO of link i becomes empty
  • FIFO of link i becomes at least half full
• TX interrupt options:
  • FIFO of link i becomes empty
  • FIFO of link i becomes less than half full