v1.7.1

What's Changed

• Rework register file's "zero" register by @stnolting in #298
• 🧹 [rtl] CPU frontend cleanup by @stnolting in #299
• [rtl] make CPU front-end synchronous by @stnolting in #300
• [rtl] optimize CPU barrel shifter timing by @stnolting in #301
• VHDL code clean-ups by @stnolting in #303
• Processor check edits by @stnolting in #304
• [rtl] optimize CPU mul/div unit by @stnolting in #305
• ✨ [rtl] add simple branch prediction by @stnolting in #306

ℹ️ See CHANGELOG.md for more details.

Full Changelog: v1.7.0...v1.7.1