[rtl] make CPU front-end synchronous #300
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* shortening critical path (memory system) * reducing area costs
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This is just another optimization PR that turns the CPU's front-end (instruction fetch engine) into a synchronous state machine. This shortens the critical path of the memory system (central memory/peripheral bus) and also reduces area costs.
🎉 reaching >130MHz on an Intel Cyclone IV FPGA (medium SoC configuration) without constraints