⚠️ Rework FIRQ System (re-rework): use MIP to clear/ack IRQs

[stnolting]

This a rework of the Fast Interrupt Requests (FIRQ) system (a remake of #176).

Old Version (Current State)

The current FIRQ system implements module-specific mechanisms to clear/acknowledge pending FIRQs. For example a pending UART RX interrupt can be acknowledged by either writing to the UART control register or by reading from the UART's RX FIFO.

New Version (This PR)

This PR aims to provide a uniform way of acknowledging FIRQs by removing the device-specific mechanisms and introducing read-write capabilities for the CPU's mip CSR.

📚 The RISC-V privilege spec. allows mip to be read-write and to clear a pending interrupt by writing '1' to the according bit position.

Example for the new FIRQ triggering (UART RX FIRQ):

1. The UART is enabled.
2. The UART RX interrupt mode (NEORV32_UART0.CTRL UART_CTRL_RX_IRQ) is configured to '1' ("FIFO at least half-full").
3. The RX FIFO's fill level reaches "half-full" level.
4. A single-shot interrupt request is sent to the CPU.
5. The CPU buffers the FIRQ if the according mie CSR bit is set.
6. The pending FIRQ gets executed; the according interrupt handler is started.
7. new: it is the task of the interrupt handler to clear/acknowledge the pending FIRQ by setting the according bit in the mip register.

The new FIRQ system simplifies the interrupt logic inside the peripheral modules. Furthermore, this concept allows more flexibility as the programmer can decide on which conditions a pending interrupt is actually cleared.

⚠️ Backwards Compatibility

• The GPTMR_CTRL_ALARM bit of the general purpose timer's (GPTMR) control register has been removed.
• The interrupt mode configuration bits of the SLINK (SLINK_IRQ_RX_MODE and SLINK_IRQ_TX_MODE) have been inverted.
• Interrupt handler (even if they are called from the NEORV32 Run-Time Environment) have to clear the triggering FIRQ by writing 1 to the according mip CSR bit.