[rtl/core] make FIRQs level-triggered

[stnolting]

This PR is a makeover of the processor's fast interrupts (FIRQ) interrupt system.

Old Version (Current State)

The current version of the CPU uses an internal interrupt queue to store fast interrupt request from the processor-internal peripherals. Currently, these request are single-shot (high for exactly one cycle) and are stored in the CPU queue until acknowledge by the hardware (before executing the trap handler).

New Version (This PR)

The reworked version uses level-triggered FIRQs that behave like the standard RISC-V interrupt (i.e. the MTIME machine timer interrupt):

• as soon as the interrupt conditions of a peripheral is met, the peripheral sets it's FIRQ line high
• the FIRQ appears in the CPU mip (machine interrupt pending) register
• the interrupt request stays pending until explicitly acknowledged by the software (just like the MTIME interrupt)
• acknowledging is done by reading/writing a peripheral-specific memory-mapped register

💡 Goals

• uniform interrupt handling for all interrupts
• more straightforward definition of interrupt condition: an IRQ is pending - and will be executed again and again - as long as the according device is fulfilling it's interrupt condition (like a FIFO that is not at least half-full yet)
• comply with RISC-V specs.
• reduce area footprint

Affected peripheral devices

• WDT (FIRQ 0)
• CFS (FIRQ 1)
• UART0 (FIRQ 2, 3)
• UART1 (FIRQ 4, 5)
• SPI (FIRQ 6)
• TWI (FIRQ 7)
• XIRQ (FIRQ 8)
• NEOLED (FIRQ 9)
• SLINK (FIRQ 10, 11)

⚠️ Backwards Compatibility

• peripheral devices will send an interrupt request right after being enabled; for example: the SPI module will send a FIRQ as long as it is in idle state (waiting for the CPU to trigger a new transmission)
• pending interrupts have to be explicitly acknowledged; the according mip bit will remain set until the interrupt request is cleared (clearing and re-enabling mie bits will not clear any pending IRQs anymore)