🐛 [rtl/core] fix bug in mip CSR clear/acknowledge #280
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software has to write ZERO to clear the according pending interrupt
stnolting
added
bug
bit needs to be CLEARED and not set
🐛 fix mip CSR write access (set ZERO to clear pending IRQ)
stnolting
changed the title
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This PR fixes a bug that has been introduced in version
1.6.4.6/ PR #236: to clear a pending interrupt application software has to write ZERO (and not one!) to the accordingmipbit (according to the RISC-V privilege architecture specifications). Hence, the acknowledge/clear mask needs to be inverted.